William Stallings Computer Organization and Architecture 6th Edition

Presentasi berjudul: "William Stallings Computer Organization and Architecture 6th Edition"— Transcript presentasi:

1 William Stallings Computer Organization and Architecture 6th Edition
Chapter 7 Input/Output

2 Pokok pokok Penting Input/Output
Arsitektur I/O sebuah sistem komputer merupakan antar mukanya ke dunia luar. Arsitektur ini dirancang untuk menyediakan alat yang sistematis untuk mengontrol interaksi dengan dunia luar dan menyediakan sistem operasi serta informasi yang diperlukan untuk mengatur aktivitas I/O secara efektif. Terdapat tiga teknik I/O yang mendasar yaitu ; I/O terprogram, I/O interrupt driven dan Direct Memory Access.

3 Input/Output Problems
Peripheral sering menggunakan format data dan panjang word yang berbeda dengan komputer dimana dia dipasang. Kecepatan transfer data dari peripheral lebih lambat dari dari CPU dan RAM Need I/O modules

4 Jadi Diperlukan Modul I/O yang mempunyai dua fungsi utama :
Input/Output Module Jadi Diperlukan Modul I/O yang mempunyai dua fungsi utama : Antar muka ke CPU dan Memory, melalui sistem bus Antar muka ke satu atau lebih peripherals dengan link data yang sesuai

5 Model umum Modul I/O

6 External Devices (Perangkat-perangkat eksternal)
Perangkat eksternal secara luas digolongkan kedalam 3 kategori : Human readable (terbaca oleh manusia) : sesuai untuk melakukan komunikasi dengan pengguna komuter. Contoh : Screen, printer, keyboard Machine readable (terbaca oleh mesin): sesuai untuk melakukan komunikasi dengan peralatan Disk magnetik, sistem pita, sensor, actuator, dll. Communication (komunikasi) : sesuai untuk melakukan komunikasi dengan perangkat yang jauh. Modem Network Interface Card (NIC)

7 Block Diagram Perangkat Eksternal

8 Typical I/O Data Rates

9 Fungsi Modul-Modul I/O
Control & Timing: (untuk mengkoordinasikan lalu lintas antara sumber daya internal dan perangkat eksternal) CPU Communication Device Communication Data Buffering Error Detection

10 I/O Steps Sebagai contoh: kontrol Transfer data dari sebuah perangkat eksternal ke prosesor dapat melibatkan langkah-langkah sbb: CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device (perangkat eksternal) I/O module transfers data to CPU

11 Diagram Blok Module I/O

12 Input Output Techniques
Programmed ( I/O Terprogram) Interrupt driven Direct Memory Access (DMA)

13 CPU has direct control over I/O
Programmed I/O CPU has direct control over I/O Sensing status Read/write commands Transferring data CPU waits for I/O module to complete operation Wastes CPU time

14 Programmed I/O - detail
CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later

15 CPU issues command (Ada 4 jenis perintah I/O) sbb:
I/O Commands CPU issues address Identifies module (& device if >1 per module) CPU issues command (Ada 4 jenis perintah I/O) sbb: Control - telling module what to do (memberitahukan modul tentang tugas yang harus dilakukannya). e.g. spin up disk (memutas disk, tape, cd, dll) Test - check status e.g. power? Error? Read Module transfers data via buffer from device Write Module transfers data via buffer to device

16 Addressing I/O Devices
Under programmed I/O data transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address) Contoh : Monitor pada PC

17 Lihat Gambar 7.6 di Buku Ref. Lebih jelas !
I/O Mapping Memory mapped I/O Devices and memory share an address space I/O looks just like memory read/write No special commands for I/O Contoh Keyboard, Monitor pada PC Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set Contoh: In, Out pada bahasa Rakitan Lihat Gambar 7.6 di Buku Ref. Lebih jelas !

18 Interrupt Driven I/O Menghilangkan waktu tunggu CPU => waktu menunggu I/O No repeated CPU checking of device I/O module interrupts when ready

19 Interrupt Driven I/O Basic Operation
CPU issues read command I/O module gets data from peripheral while CPU does other work I/O module interrupts CPU CPU requests data I/O module transfers data

20 Check for interrupt at end of each instruction cycle If interrupted:-
CPU Viewpoint Issue read command Do other work Check for interrupt at end of each instruction cycle If interrupted:- Save context (registers) Process interrupt Fetch data & store See Operating Systems notes

21 How do you identify the module issuing the interrupt?
Design Issues How do you identify the module issuing the interrupt? How do you deal with multiple interrupts? i.e. an interrupt handler being interrupted

22 Identifying Interrupting Module (1)
Different line for each module PC Limits number of devices Software poll CPU asks each module in turn Slow

23 Identifying Interrupting Module (2)
Daisy Chain or Hardware poll Interrupt Acknowledge sent down a chain Module responsible places vector on bus CPU uses vector to identify handler routine Bus Master / Bus Arbitrary Modul I/O harus memperoleh kontrol bus sebelum modul itu menggunakan jalur permintaan interupsi e.g. PCI & SCSI

24 Multiple Interrupts Each interrupt line has a priority Higher priority lines can interrupt lower priority lines

25 Example - PC Bus 80x86 has one interrupt line 8086 based systems use one 8259A interrupt controller 8259A has 8 interrupt lines

26 Sequence of Events 8259A accepts interrupts 8259A determines priority 8259A signals 8086 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt

27 ISA Bus Interrupt System
ISA bus chains two 8259As together Link is via interrupt 2 Gives 15 lines 16 lines less one for link IRQ 9 is used to re-route anything trying to use IRQ 2 Backwards compatibility Incorporated in chip set

28 82C59A Interrupt Controller

29 Intel 82C55A Programmable Peripheral Interface

30 Using 82C55A To Control Keyboard/Display

31 Kekurangan I/O terprogram dan I/O Interrupt Driven:
Direct Memory Access Kekurangan I/O terprogram dan I/O Interrupt Driven: Interrupt driven and programmed I/O require active CPU intervention Transfer rate is limited (dibatasi oleh kecepatan transfer I/O) Prosesor ditentukan oleh pengaturan transfer I/O. Sejumlah instruksi harus dieksekusi untuk setiap transfer I/O. DMA is the answer

32 Fungsi DMA Perlu tambahan Module DMA pada sistem bus Modul DMA mampu menirukan prosesor dan bahkan mngambil alih kontrol sistem dari prosesor. Modul DMA harus menggunakan bus hanya ketika prosesor tdk memerlukannya, atau modul DMA harus memaksa prosesor untuk menghentikan operasi untuk sementara. Teknik yang digunakan DMA sering disebut “Pencurian Siklus”, karena modul DMA pada hakekatnya mencuri siklus bus.

33 DMA Module Diagram

34 CPU kemudian melanjutkan pekerjaan yg lainnya.
DMA Operation Pada saat prosesor ingin membaca atau menulis data, prosesor mengeluarkan perintah ke modul DMA berupa informasi sbb: Read/Write yang diminta, menggunakan jalur kontrol read/write antara prosesor dan modul DMA Alamat perangkat I/O (Device address) Starting address of memory block for data Amount of data to be transferred CPU kemudian melanjutkan pekerjaan yg lainnya. DMA controller deals with transfer (tanpa melalui prosesor) DMA controller sends interrupt when finished

35 DMA Transfer Cycle Stealing (mencuri siklus)
Lihat gambar 7.12 di text book Prosesor dihentikan sesaat sebelum prosesor menggunakan bus. Modul DMA kemudian mentransfer satu word data, dan kemudian mengembalikan kontrol ke prosesor Not an interrupt CPU does not switch context CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write CPU berhenti sementara untuk satu siklus bus.

36 Single Bus, Detached DMA controller Each transfer uses bus twice
DMA Configurations (1) Single Bus, Detached DMA controller Each transfer uses bus twice I/O to DMA then DMA to memory CPU is suspended twice

37 Single Bus, Integrated DMA controller
DMA Configurations (2) Single Bus, Integrated DMA controller Controller may support >1 device Each transfer uses bus once DMA to memory CPU is suspended once

38 Bus supports all DMA enabled devices Each transfer uses bus once
DMA Configurations (3) Separate I/O Bus Bus supports all DMA enabled devices Each transfer uses bus once DMA to memory CPU is suspended once

39 Evolusi dari fungsi I/O
CPU mengontrol periferal secara langsung CPU menggunakan I/O terprogram CPU menggunakan Interupsi Modul I/O diberi akses langsung melalui DMA Modul I/O ditingkatkan kemampuannya menjadi sebuah prosesor (prosesor I/O) Prosesor I/O yg sudah dilengkapai dengan memori internal

40 I/O Channels Pada point 5-6 diatas terjadi perubahan besar dgn berhasil dibuatnya modul I/O yg mampu mengeksekusi program. Modul I/O ini sering disebut dgn Jalur I/O (I/O Channel) Merupakan perluasan dari konsep DMA Mempunyai kemampuan untuk mengeksekusi perintah I/O. CPU tdk mengeksekusi perintah I/O e.g. 3D graphics cards

41 I/O Channel Architecture

42 Interfacing (antar muka) IEEE 1394 FireWire
High performance serial bus Fast Low cost Easy to implement Also being used in digital cameras, VCRs and TV

43 FireWire Configuration
Daisy chain Up to 63 devices on single port Really 64 of which one is the interface itself Up to 1022 buses can be connected with bridges Automatic configuration No bus terminators May be tree structure

44 Simple FireWire Configuration

45 FireWire 3 Layer Stack Physical Link Transaction
Transmission medium, electrical and signaling characteristics Link Transmission of data in packets Transaction Request-response protocol

46 FireWire Protocol Stack

47 FireWire - Physical Layer
Data rates from 25 to 400Mbps Two forms of arbitration Based on tree structure Root acts as arbiter First come first served Natural priority controls simultaneous requests i.e. who is nearest to root Fair arbitration Urgent arbitration

48 Two transmission types
FireWire - Link Layer Two transmission types Asynchronous Variable amount of data and several bytes of transaction data transferred as a packet To explicit address Acknowledgement returned Isochronous Variable amount of data in sequence of fixed size packets at regular intervals Simplified addressing No acknowledgement

49 FireWire Subactions

50 I/O specification aimed at high end servers
InfiniBand I/O specification aimed at high end servers Merger of Future I/O (Cisco, HP, Compaq, IBM) and Next Generation I/O (Intel) Version 1 released early 2001 Architecture and spec. for data flow between processor and intelligent I/O devices Intended to replace PCI in servers Increased capacity, expandability, flexibility

51 InfiniBand Architecture
Remote storage, networking and connection between servers Attach servers, remote storage, network devices to central fabric of switches and links Greater server density Scalable data centre Independent nodes added as required I/O distance from server up to 17m using copper 300m multimode fibre optic 10km single mode fibre Up to 30Gbps

52 InfiniBand Switch Fabric

53 InfiniBand Operation 16 logical channels (virtual lanes) per physical link One lane for management, rest for data Data in stream of packets Virtual lane dedicated temporarily to end to end transfer Switch maps traffic from incoming to outgoing lane

54 InfiniBand Protocol Stack

55 Foreground Reading Check out Universal Serial Bus (USB) Compare with other communication standards e.g. Ethernet