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S HIFT R EGISTER S ERIAL C OMMUNICATION System Digital 1.

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Presentasi berjudul: "S HIFT R EGISTER S ERIAL C OMMUNICATION System Digital 1."— Transcript presentasi:

1 S HIFT R EGISTER S ERIAL C OMMUNICATION System Digital 1

2 P OKOK B AHASAN Shift Registers Definisi Model I/O : Serial, Pararel dan Kombinasi Arah pergeseran : Kiri, Kanan dan dua arah Applikasi/penggunaan Implementasi VHDL MSI Shift Registers Komunikasi Serial 2 DQ Input Clock DQDQDQ Q3Q3 Q2Q2 Q1Q1 Q0Q0 Enable Output

3 S HIFT R EGISTERS Memanfaatkan register untuk penyimpanan, manipulasi dan transfer (pemindahan) data 3

4 D EFINISI Register adalah sebuah rangkaian digital dengan dua (2) fungsi utama : Data storage dan Data Movement Shift register menyediakan fungsi data movement A shift register “shifts” its output once every clock cycle Shift register adalah sekelompok flip flop yang dipasang secara linier dengan masukan dan keluaran saling disambungkan satu dengan yang lain, sehingga data akan digeser dari satu alat ke alat yang lain ketika rangkaian tersebut diaktifkan 4

5 P EMANFAATAN S HIFT REGISTER 5 Komunikasi UART -> Universal asynchronous receiver/transmitter Konversi antara serial dan pararel Penyimpanan sementara di processor scratch-pad memories Operasi Aritmatika Perkalian, pembagian Applikasi counter Johnson counter ring counter LSFR counters time delay devices more …

6 S HIFT R EGISTER C HARACTERISTICS Tipe Serial-in, Serial-out Serial-in, Parallel-out Parallel-in, Serial-out Parallel-in, Parallel-out Universal Arah Left shift Right shift Rotate (right or left) Bidirectional 6 n-bit shift register

7 D ATA M OVEMENT Bit – bit dalam shift register dapat digeser sesuai gambar dibawah ini 7

8 n-bit shift register D ATA M OVEMENT Blok diagram shift register dengan berbagai variasi input/output 8 n-bit shift register

9 S ERIAL -I N S ERIAL -O UT Bit data masuk satu persatu dan keluar satu per satu Satu flip flop bertugas untuk menyimpan satu data Pergerakan data dapat geser kiri / kanan, pada umumnya satu register hanya bisa satu arah. Masukan Asynchronous preset dan clear digunakan untuk set nilai awal 9

10 S ERIAL -I N S ERIAL -O UT Rangkaian logika ini menunjukkan gambar secara umum Serial in Serial Out Shift Register Menggunakan SR Flip Flop Dirangkai sehingga memiliki perilaku seperti flip-flop D Nilai masukan input akan digeser ke setiap flip-flop berpadanan dengan clock pulse 10 N-Bit Shift Register 0N 1

11 S HIFT R EGISTERS Shift register paling sederhana hanya menggunakan flip-flops Keluaran dari flip-flop disambungkan dengan masukan D pada flip- flop berikutnya di sebelah kanan Setiap pulsa clock akan menggeser nilai register satu bit satu posisi ke sebelah kanan Serial input (SI) menentukan status masukan Flipflop paling kiri pada saat terjadinya pergeseran, Serial output (SO) diambil dari keluaran flipflop paling kanan Perhatikan animasi 11 Q Q Q Q

12 S ERIAL -I N S ERIAL -O UT Cara paling mudah untuk mempelajari adalah lihat ilustrasi pada sebelah kanan 4 bit data word “1011” akan di geser pada 4 bit shift register One shift per clock pulse Data di tunjukkan masuk dari sisi sebelah kiri dan keluar dari sisi kanan

13 S ERIAL -I N S ERIAL -O UT Diagram di sebelah kanan menunjukkan urutan 4 bit “1010” di load ke 4 bit SISO shift register Setiap bit akan bergeser 1 posisi ke sebelah kanan pada setiap terjadi clock leading edge dibutuhkan 4 pulsa clock untuk memasukkan seluruh bit ke register. 13

14 S ERIAL -I N S ERIAL -O UT Diagram disebelah kanan menunjukkan urutan 4 bit “1010” unloaded dari 4 bit SISO shift register Setiap bit akan bergerak satu bit ke kanan setiap signal clock Dibutuhkan 4 clock untuk mengakhiri proses tersebut. 14

15 S ERIAL -I N S ERIAL -O UT SISO di pergunakan untuk komunikasi data : RS-232 modem transmission and reception Ethernet links SONET etc. 15

16 S ERIAL -I N S ERIAL -O UT IN VHDL Berikut ini adalah kode program implementasi VHDL untuk 8 bit shift register pada positif edge clock Serial in Serial Out 16 library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7); end archi;

17 K ONVERSI S ERIAL - TO -P ARALLEL Konversi serial ke pararel dibutuhkan pada saat Misal setelah menerima transmisi data secara serial Ilustrasi 4 bit serial in pararel out Shift register di gambarkan di sebelah kanan Output Q pada flipflop paling kanan juga dapat berfungsi sebagai serial out. 17 n-bit shift register

18 S ERIAL - TO -P ARALLEL C ONVERSION Digunakan serial in pararel out shift register sepanjang N untuk mengubah N bit word dari serial ke pararel. Di butuhkan pulsa N clock untuk load dan 1 clock pulse untuk unload 18

19 S ERIAL - TO -P ARALLEL C ONVERSION Dua buah shift register di sebelah kanan digunakan konversi serial data ke pararel data Register bagian bawah akan menyediakan untuk register bagian atas, ketika di geser oleh register bag bawah 19

20 P ARALLEL - TO -S ERIAL C ONVERSION Data di applikasikan ke bentuk pararel, kemudian di umpan masukkan ke Pin A hingga D. Kemudian dibaca secara sequential pada register 1 bit pada satu waktu dari PA ke PD setiap 1 siklus clock dalam bentuk serial Satu pulsa clock untuk load Empat pulsa clock untuk unload 20 n-bit shift register

21 P ARALLEL - TO -S ERIAL C ONVERSION Logic circuit for a parallel-in, serial-out shift register 21 Mux-like

22 P ARALLEL -I N P ARALLEL -O UT Parallel-in Parallel-out Shift Registers can serve as a temporary storage device or as a time delay device The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked One clock pulse to load One pulse to unload 22

23 n-bit shift register U NIVERSAL S HIFT R EGISTER Universal shift register Can do any combination of parallel and serial input/output operations Requires additional inputs to specify desired function Uses a Mux-like input gating 23 L/S A B A B F

24 U NIVERSAL S HIFT R EGISTER Parallel-in, parallel-out shift register 24 Mux-like

25 U NIVERSAL S HIFT R EGISTER Parallel shift register (can serve as converting parallel-in to serial-out shifter): 25

26 MSI S HIFT R EGISTERS 74LS164 is an 8-Bit Serial-In Parallel-Out Shift Register Typical Shift Frequency of 35 MHz Asynchronous Master Reset Gated Serial Data Input Fully Synchronous Data Transfers 26

27 MSI S HIFT R EGISTERS 74LS164 8-Bit Serial-In Parallel-Out Shift Register 27

28 MSI S HIFT R EGISTERS The 74LS164 is an edge-triggered 8- bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input an unused input must be tied HIGH, or both inputs connected together 28

29 MSI S HIFT R EGISTERS Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right This also enters into Q 0 the logical AND of the two data inputs (AB) that existed before the rising clock edge. 29

30 MSI S HIFT R EGISTERS 74LS164 logic diagram 30 A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.

31 MSI S HIFT R EGISTERS 74LS166 is an 8-Bit Shift Register Parallel-in or serial-in shift/load input establishes the parallel-in or serial-in mode Serial-out Synchronous Load Serial data flow is inhibited during parallel loading Direct Overriding Clear 31

32 MSI S HIFT R EGISTERS 74LS166 is an 8-Bit Shift Register 32

33 MSI S HIFT R EGISTERS 74LS166 8-Bit Shift Register is a parallel-in or serial-in, serial-out shift register 33

34 MSI S HIFT R EGISTERS 74LS166 is an 8-Bit Shift Register 34

35 MSI S HIFT R EGISTERS 74LS166 is an 8-Bit Shift Register 35

36 MSI S HIFT R EGISTERS 74LS194 4-Bit Bidirectional Universal Shift Register may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers 36

37 MSI S HIFT R EGISTERS 74LS194 4-Bit Bidirectional Universal Shift Register 37

38 MSI S HIFT R EGISTERS 74LS194 control inputs S1 and S0 38

39 MSI S HIFT R EGISTERS 74LS194 4-Bit Bidirectional Universal Shift Register

40 MSI S HIFT R EGISTERS 74LS194 4-Bit Bidirectional Universal Shift Register 40

41 “U NIVERSAL ” SHIFT REGISTER 74 X 194 Shift left Shift right Load Hold 41

42 MSI S HIFT R EGISTERS One stage of the 74x194 42

43 VHDL D HIFT R EGISTER Universal shift register design The 3-bit function select determines the operation of the register Serial in and Parallel load available 43 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Vshftreg is port (CLK, CLR, RIN, LIN: in STD_LOGIC; S: in STD_LOGIC_VECTOR (2 downto 0); -- function select D: in STD_LOGIC_VECTOR (7 downto 0); -- data in Q: out STD_LOGIC_VECTOR (7 downto 0) -- data out); end Vshftreg; architecture Vshftreg_arch of Vshftreg is signal IQ: STD_LOGIC_VECTOR (7 downto 0); begin process (CLK, CLR, IQ) begin if (CLR='1') then IQ '0'); elsif (CLK'event and CLK='1') then case CONV_INTEGER(S) is when 0 => null; -- Hold when 1 => IQ <= D; -- Load when 2 => IQ <= RIN & IQ(7 downto 1); -- Shift right when 3 => IQ <= IQ(6 downto 0) & LIN; -- Shift left when 4 => IQ <= IQ(0) & IQ(7 downto 1); -- Shift circular right when 5 => IQ <= IQ(6 downto 0) & IQ(7); -- Shift circular left when 6 => IQ <= IQ(7) & IQ(7 downto 1); -- Shift arithmetic right when 7 => IQ <= IQ(6 downto 0) & '0'; -- Shift arithmetic left when others => null; end case; end if; Q <= IQ; end process; end Vshftreg_arch;

44 MSI S HIFT R EGISTERS 74LS299 is an 8-bit universal shift/storage register with 3-state outputs Four modes of operation are possible: hold (store) shift left shift right load data 44

45 MSI S HIFT R EGISTERS 74LS299 universal shift/storage register 45

46 MSI S HIFT R EGISTERS 74LS299 universal shift/storage register 46 S0 S1 D Q CP CD

47 MSI S HIFT R EGISTERS 74LS299 logic circuit diagram: The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q0 and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register. 47

48 S ERIAL C OMMUNICATIONS A practical application of Registers / Shift Registers 48

49 S ERIAL DATA SYSTEMS ( E. G., TPC) Read discussion and study circuits in text. 49

50 S ERIAL D ATA T RANSMISSION Parallel-to-serial conversion for serial transmission 50 serial transmission media in: parallel data out: parallel data Destination module Source module

51 S ERIAL DATA IN THE PHONE SYSTEM (E-1) Mb/s links between phone switches and subscribers partitioned into Kb/s channels Each channel gets a timeslot in a “frame” where it can send 8 bits every 125  sec frames/sec 51

52 T IMESLOT DETAILS 52 count = 255

53 P ARALLEL - TO - SERIAL CONVERSION 53  256 LSBs are bit number Assert shift-register LOAD input during bit 7 Timeslot number can be decoded and used to select source of parallel data Serial data to destination count = 255

54 S ERIAL - TO - PARALLEL CONVERSION 54 Synchronize destination’s counter to source’s Shift in serial data Detect that a complete byte has been received Holding register for complete byte Note: loads 0…0

55 D ESTINATION TIMING 55 Serial-in, parallel-out shift register outputs Holding-register outputs Grab complete byte when available

56 S ERIAL COMMUNICATION ON ONE WIRE Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one “wire” is used. How? One solution: Manchester code. 56 Or use a phase-locked loop (analog circuit) to extract clock from the data:

57 S TILL A COUPLE OF PROBLEMS Framing -- SYNC signal Solution: Use a unique data pattern for SYNC PLL clock recovery -- what if too many zeroes are transmitted? PLL can’t stay in sync. Solution: Use a code that guarantees a minimum number of ones Phone system: Map > (creating slight voice distortion) Gigabit Ethernet: Uses 8B10B code, solving both problems Map each byte into 8 bits Use only a “good” subset of 2 10 code words Use another code word for synchronization 57

58 A SSIGNMENTS Completed Part 2 Midterm problems due Wednesday Continue working on the MIPS project Description available on the course web page 58


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