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RANGKAIAN LOGIKA KOMBINASIONAL Pertemuan 8 & 9 Dosen : I Made Astawa.

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Presentasi berjudul: "RANGKAIAN LOGIKA KOMBINASIONAL Pertemuan 8 & 9 Dosen : I Made Astawa."— Transcript presentasi:

1 RANGKAIAN LOGIKA KOMBINASIONAL Pertemuan 8 & 9 Dosen : I Made Astawa

2 RANGKAIAN LOGIKA KOMBINASIONAL PENDAHULUAN Suatu rangkaian diklasifikasikan sebagai kombinasional jika memiliki sifat yaitu keluarannya ditentukan hanya oleh masukkan eksternal saja. Suatu rangkaian diklasifikasikan sequential jika ia memiliki sifat keluarannya ditentukan tidak hanya oleh masukkan eksternal tetapi juga oleh kondisi sebelumnya.

3 PROSEDUR PERANCANGAN a.Pokok permasalahan sudah ditentukan yaitu jumlah input yang dibutuhkan serta jumlah output yang tertentu. b.Susun kedalam tabel kebenaran (Truth Table). c.Kondisi don’t care dapat diikut sertakan apabila tidak mempengaruhi output. d.Sederhanakan fungsi output dengan K-Map atau Metode Tabulasi e.Gambar Rangkain logikanya

4 DECODER Decoder adalah rangkaian kombinasi yang akan memilih salah satu keluaran sesuai dengan konfigurasi input. Decoder memiliki n input dan 2 n output. Blok Diagram Decoder. Decoder n to 2 n IOIO I1I1 InIn YOYO Y1Y1 Y (2n-1)

5 DECODER Untuk Decoder 2 to 4 Decoder n to 2 n IOIO I1I1 YOYO Y1Y1 Y2Y2 Y3Y3

6 DECODER Tabel Kebenaran Untuk Decoder 2 to 4 I O I 1 Y O Y 1 Y 2 Y 3 O O O 1 1 O O O O O 1 O O O O 1 O O O O 1

7 DECODER 2 To 4 I1I1 I0I0 Y0Y0 Y1Y1 Y2Y2 Y3Y3

8 1-to-2-Line Decoder 2-to-4-Line Decoder  Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates. Decoder Examples A A D D D D (a) D 0 A 1 A 0 D 1 A 1 A 0 D 2 A 1 A 0 D 3 A 1 A 0 (b) A 1 A 0

9 Decoder Expansion - Example 1

10 In general, attach m-enabling circuits to the outputs See truth table below for function –Note use of X’s to denote both 0 and 1 –Combination containing two X’s represent four binary combinations Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputs In this case, called a demultiplexer Decoder with Enable

11 HALF ADDER ( HA ) Tabel kebenaran Simbol Half Adder I N P U TO U T P U T ABS (Sum)C (Carry) HA A CB S Dimana : A B C S +

12 HALF ADDER ( HA ) Persamaan output Untuk Sum S = AB’ + A’B = A  B Untuk Carry C = AB 10A’ 01A BB’ 00A’ 10A BB’

13 HALF ADDER Beberapa macam implementasi dari Half Adder: S = (x + y)(x’ + y’) C = x y S = (C + x’ y’)’ C = x y S = (x + y)(x’ + y’) C = (x’ + y’)’ Rangkaian Logika nya Lihat di Papan Tulis !

14 Implementations: Half-Adder The most common half adder implementation is: A NAND only implementation is: YXC YXS   )(C C)YX(S )YX(    X Y C S X Y C S

15 Full-Adder A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. –For a carry-in (Z) of 0, it is the same as the half-adder: –For a carry- in (Z) of 1: Z0000 X Y C S Z1111 X Y C S

16 Full-Adder Simbol Full Adder F A A B Cin S Co Cin A B Co S +

17 Logic Optimization: Full-Adder Full-Adder Truth Table: Full-Adder K-Map: XYZCS X Y Z S X Y Z C

18 Equations: Full-Adder From the K-Map, we get: The S function is the three-bit XOR function (Odd Function): The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if the sum is 1 and a carry-in (Z) occurs. Thus C can be re-written as: The term X·Y is carry generate. The term X  Y is carry propagate. ZYZXYXC ZYXZYXZYXZYXS   ZYXS  Z)YX(YXC 

19 Full Adder Full Adder Schematic Here X, Y, and Z, and C (from the previous pages) are A, B, C i and C o, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for S)) and Carry logic (for C o ): (G = Generate) OR (P =Propagate AND C i = Carry In) Co  G + P · Ci AiAi BiBi CiCi C i+1 GiGi PiPi SiSi

20 Full Adder dgn 2 buah HA Atau HA Cin A B S Co

21 Contoh. Implementasikan suatu Full Adder dengan memakai Decoder dan 2 gerbang OR Jawab : Sum = A  B  Cin = Σ 1,2,4,7 Carry out = (A  B) Cin + AB = Σ 3,5,6,7 FULL ADDER DGN DECODER

22 Gambar Rangkaian Logika Decoder 3 to 8 Cin A B Y1Y1 Y0Y0 Y2Y2 Y3Y3 Y4Y4 Y5Y5 Y6Y6 Y7Y7 Sum Carry out

23 4-bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four 1- bit Full Adders:

24 2’s Complement Adder/Subtractor Subtraction can be done by addition of the 2's Complement. 1. Complement each bit (1's Complement.) 2. Add 1 to the result. The circuit shown computes A + B and A – B: For S = 1, subtract, the 2’s complement of B is formed by using XORs to form the 1’s comp and adding the 1 applied to C 0. For S = 0, add, B is passed through unchanged

25 Code Conversion Konversi 8421BCD ke Excess-3

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28 A B C D W X Y Z

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30 LATIHAN MERANCANG DECODER Rancang 8421BCD to seven segment ? Catatan : Seven Segment. a d g b c f e


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