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1 Pertemuan 12 Arithmetic Network di VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01.

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Presentasi berjudul: "1 Pertemuan 12 Arithmetic Network di VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01."— Transcript presentasi:

1 1 Pertemuan 12 Arithmetic Network di VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2 2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menerapkan gerbang logik, switching logik, dan atau struktur deskripsi Verilog untuk membangun rangkaian arithmetic sederhana dalam CMOS VLSI.

3 3 Bit Adder = = = = 10 operasi adder x y s c half adder HA x y s c simbol x y s c rangkaian module half_adder_gate (sum, c_out, x, y) ; input x, y ; output sum, c_out ; and (c_out, x, y) ; xor (sum, x, y) ; endmodule Verilog HDL:

4 4 Bit Adder a = a 3 a 2 a 1 a 0 b = b 3 b 2 b 1 b 0 a3a2a1a0b3b2b1b0a3a2a1a0b3b2b1b0 + c 4 s 3 s 2 s 1 s 0 a + b: ciaibisiciaibisi c i+1 + FA (+) a i b i cici c i+1 sisi a i b i c i s i c i s i = a i  b i  c i c i+1 = a i. b i + c i. (a i  b i )

5 5 Bit Adder rangkaian a i b i c i+1 cici sisi HA a i b i c i+1 cici sisi module full_adder_HA (sum, c_out, a, b, c_in) ; input a, b, c_in ; output sum, c_out ; wire wa, wb, wc ; half_adder_gate (wa, wb, a, b) ; half_adder_gate (sum, wc, wa, c_in) ; or (c_out, wb, wc) ; endmodule Verilog HDL:

6 6 Ripple Carry Adder Adder n n ab n s cncn + a 2 b 2 s2s2 + a 3 b 3 s3s3 + a 0 b 0 s0s0 + a 1 b 1 s1s1 c0c0 c1c1 c2c2 c3c3 c4c4 4-bit ripple carry adder circuit module four_bit_adder (sum, c_4, a, b, c_0) ; input [3:0] a, b ; input c_0 ; output [3:0] sum ; output c_4 ; assign {c_4, sum} = a + b + c_0 ; endmodule Verilog HDL:

7 7 Carry Look Ahead Adder g i = 1 p i = 1 aiai bibi cici C i+1 sisi gigi pipi a i. b i a i  b i a i = b i = 0 a i = b i = 1 a i  b i Basic Carry Look Ahead Algorithm

8 8 Multiplier Dasar operasi: 0 x 0 = 0 0 x 1 = 0 1 x 0 = 0 1 x 1 = 1 Perkalian dilakuan dengan cara menuliskan kembali bilangan yang dikali jika bit bilangan pengalinya “1”, dengan penulisan LSB dari bilangan yang dikali ditulis dibawah bit “1” pengali bersangkutan. Kemudian hasil perkalian adalah penjumlahan penulisan kembali bilangan yang dikali tersebut. Contoh: x 5x

9 9 Multiplier n-bit adder MUX multiplicandmultiplier n n n n n shr  Product register (2n) Register-based multiplier network 0

10 10 Array Multiplier P7P6P5P4P3P2P1P0P7P6P5P4P3P2P1P0 b0b1b2b3b0b1b2b3 a 3 a 2 a 1 a 0 Multiplier Array a2b0a2b0 a3b0a3b0 a0b0a0b0 a1b0a1b0 a2b1a2b1 a3b1a3b1 a0b1a0b1 a1b1a1b1 a2b2a2b2 a3b2a3b2 a0b2a0b2 a1b2a1b2 a2b3a2b3 a3b3a3b3 a0b3a0b3 a1b3a1b3 p7p7 p6p6 p5p5 p4p4 p3p3 p2p2 p1p1 p0p0

11 11 RESUME Bit Adder: Half Adder, Full Adder. Ripple Carry Adder. Carry Look ahead adder. Multiplier


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