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1 Pertemuan 23 Basic Processing Unit: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1.

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Presentasi berjudul: "1 Pertemuan 23 Basic Processing Unit: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1."— Transcript presentasi:

1 1 Pertemuan 23 Basic Processing Unit: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

2 2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Mendesain microprogramming untuk instruksi Microprocessor ( C5 ) ( No TIK : 11 )

3 3 Chapter 7. Basic Processing Unit: I

4 4

5 5 BA Z ALU Y in Y Z Z out Ri in Ri Ri out bus Internal processor Constant 4 MUX Figure 7.2. Input and output gating for the registers in Figure 7.1. Select

6 6 Figure 7.3. Input and output gating for one register bit.

7 7 Figure 7.4. Connection and control signals for register MDR.

8 8

9 9

10 10 StepAction 1PC out,MAR in,Read,Select4,Add,Z in 2Z out,PC in,Y,WMFC 3MDR out,IR in 4Offset-field-of-IR out,Add,Z in 5Z out,PC in,End Figure 7.7. Control sequence for an unconditional branch instruction.

11 11 StepAction 1PC out,R=B,MAR in,Read,IncPC 2WMFC 3MDR outB,R=B,IR in 4R4 outA,R5 outB,SelectA,Add,R6 in,End Figure 7.9.Control sequence for the instruction. Add R4,R5,R6, for the three-bus organization in Figure 7.8.

12 12 Figure Control unit organization. CLK Clock Control step IR encoder Decoder/ Control signals codes counter inputs Condition External

13 13

14 14 Pertemuan 1 Basic Processing Unit: II Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

15 15 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Mendesain microprogramming untuk instruksi Microprocessor ( C5 ) ( No TIK : 11 )

16 16 Chapter 7. Basic Processing Unit: II

17 17 Figure Generation of the Z i n control signal for the processor in Figure 7.1. T 1 Add Branch T 4 T 6

18 18

19 19

20 20

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22 22 AddressMicroinstruction 0PC out,MAR in,Read,Select4,Add,Z in 1Z out,PC in,Y,WMFC 2MDR out,IR in 3Branchtostartingaddressofappropriatemicroroutine IfN=0,thenbranchtomicroinstruction0 26Offset-field-of-IR out,SelectY,Add,Z in 27Z out,PC in,End Figure Microroutine for the instruction Branch<0.

23 23 OP code010RsrcRdst Mode Contents of IR Figure 7.21.Microinstruction for Add (Rsrc)+,Rdst. Note: Microinstruction at location 170 is not executed for this addressing mode. AddressMicroinstruction (octal) 000PC out, MAR in, Read, Select 4, Add, Z in 001Z out, PC in, Y in, WMFC 002MDR out, IR in 003  Branch {  PC  101 (from Instruction decoder);  PC 5,4  [IR 10,9 ];  PC 3  121Rsrc out, MAR in, Read, Select4, Add, Z in 122Z out, Rsrc in MDR out, MAR in, Read, WMFC 171MDR out, Y in 172Rdst out, SelectY, Add, Z in 173Z out, Rdst in, End [IR 10 ]  [IR 9 ]  8 ]}  Branch {  PC  170;  PC 0  [IR 8 ]}, WMFC

24 24

25 25 Figure P7.1. Organization of shift-register control for Problem 7.22.

26 26 Clock A B X Y Z Figure P7.2. Digital controller in Problem 7.23.


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