Fernando Ardilla Pertemuan 1
outline Kontrak perkuliahan Pengenalan VHDL
Kontrak perkuliaan UTS : 35% UAS : 35% Tugas : 20% Sikap / keaktifan di kelas: 10%
Design Unit – all Package, library Arsitektur modeling Contant Signal VHDL operator Cuncurent signal ○ Simple ○ Conditional ○ Select Sequentiial ○ f then ○ Case ○ Loop ○ Wait Kasus Eqivalen Variable Data type RTL Component