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Pertemuan 25 Pipelining: I

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Presentasi berjudul: "Pertemuan 25 Pipelining: I"— Transcript presentasi:

1 Pertemuan 25 Pipelining: I
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1 Pertemuan 25 Pipelining: I

2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Mengkombinasikan Metode Pipeline dalam mendesain sistem komputer ( C5 ) ( No TIK : 12 )

3 Chapter 8. Pipelining: I

4 Figure 8.1. Basic idea of instruction pipelining.
ime I I I 1 2 3 F E F E F E 1 1 2 2 3 3 (a) Sequential execution Interstage buffer B1 Instruction Ex ecution fetch unit unit (b) Hardware organization T ime Clock cycle 1 2 3 4 Instruction I F E 1 1 1 I F E 2 2 2 I F E 3 3 3 (c) Pipelined execution Figure 8.1. Basic idea of instruction pipelining.

5 100 Move N,R1 104 Move #NUM1,R2 108 Clear R0 LOOP 112 Add (R2),R0 116 Add #4,R2 120 Decrement R1 124 Branch>0 LOOP 128 Move R0,SUM 132 SUM 200 N 204 100 NUM1 208 NUM2 212 NUM n 604

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12 Figure 8.6. Pipeline stalled by data dependency between D2 and W1.

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14 Instruction fetch unit
Instruction queue F : Fetch instruction D : Dispatch/ E : Ex ecute W : Write Decode instruction results unit Figure Use of an instruction queue in the hardware organization of Figure 8.2b.

15 Figure 8.11. Branch timing in the presence of an instruction queue.
ime Clock c ycle 1 2 3 4 5 6 7 8 9 10 Queue length 1 1 1 1 2 3 2 1 1 1 F D E E E W I 1 1 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E W 4 4 4 4 4 I (Branch) F D 5 5 5 I F X 6 6 I F D E W k k k k k I F D E k+ 1 k+ 1 k+ 1 k+ 1 Figure Branch timing in the presence of an instruction queue. Branch target address is computed in the D stage.

16 Pertemuan 26 Pipelining: II
Matakuliah : T0324 / Arsitektur dan Organisasi Komputer Tahun : 2005 Versi : 1 Pertemuan 26 Pipelining: II

17 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Mengkombinasikan Metode Pipeline dalam mendesain sistem komputer ( C5 ) ( No TIK : 12 )

18 Chapter 8. Pipelining: II

19 Pipelining Fetch instruction Decode instruction
Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result Overlap these operations 38

20 Two Stage Instruction Pipeline

21 Timing of Pipeline 39

22 Branch in a Pipeline 40

23 Six Stage Instruction Pipeline

24 Alternative Pipeline Depiction

25 Speedup Factors with Instruction Pipelining


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