FIELD EFFECT TRANSISTOR

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1 FIELD EFFECT TRANSISTOR
Bahan Kuliah Elektronika Dasar Pertemuan ke 11 FIELD EFFECT TRANSISTOR oleh Ir.Bambang Sutopo,M.Phil Jurusan Teknik Elektro FT-UGM 2007

2 DRIVER RELAY (diskusi tugas lalu)
DIODA freewheel VCC IB-JENUH = arus basis yang membuat transistor dalam kondisi jenuh. RB Relay membutuhkan arus sekitar 50 sampai 100 mili Amper

3 TRANSISTOR SBG BUFER OP-AMP
Input 1 relay + R Input 2 _ R harus bisa membatasi arus agar arus yang dikeluarkan op-amp tak terlalu besar. R harus masih dapat membuat transistor jenuh.

4 Pilihan R tergantung kemampuan IC mengeluarkan arus (source) atau dimasuki arus (sink)
relay 100mA R relay 200mA relay

5 Eka Ardi Daerah Tak stabil

6 Eka Ardi

7

8 IB 1 2 VCE 3

9 LM 339/239 VCC Rpull-up Beban OPEN COLLECTOR

10 12V OR 1K + _ + _

11 12V 4,7K 1K + 8,2K _ Lampu Vin 12V + 4,7K _ 1K

12

13 IC 555

14 LM 741

15 LM 358

16 TOTEM POLE OUTPUT LM 358

17 SOURCE CURRENT

18 SINK CURRENT

19 LM 124/234/324

20 IC 555

21 PROYEK KITA relay R DIODA FOTO KOMPARATOR SCHMITT

22 Field Effect Transistor - FET
Mengapa kita masih perlu transistor jenis lain? BJT mempunyai sedikit masalah. BJT selalu memerlukan arus basis IB, walaupun arus ini kecil, tetapi tidak bisa diabaikan, terutama sekali saat BJT digunakan sebagai saklar, pasti dibutuhkan arus yang cukup besar untk membuat transistor jenuh.

23 Field Effect Transistor - FET
Apakah ada jenis transistor lain yang bisa digerakkan dengan tegangan tanpa membutuhkan arus ? Jawabannya ada di FET. Dengan perantaraan FET, kita dapat menghubungkan peralatan komputer atau transduser yang tidak bisa menghasilkan arus, dengan alat yang lebih besar. FET bisa digunakan sbg bufer, sehingga tidak membutuhkan arus dari komputer/trasduser. Teknologi modern pembuatan IC, ternyata dimensi transistor FET bisa dibuat sangat kecil, sehingga pembuatan IC saat ini berdasarkan transistor FET ini.

24 FET vs BJT BJT FET Base (B) Gate (G) Collector (C) Drain(D)
Emitter (E) Base current Collector current Collector-Emitter Voltage FET Gate (G) Drain(D) Source(S) Gate Voltage Drain current Drain-source voltage

25 Jenis-jenis FET JFET (Junction FET) MOSFET (Metal Oxide Silikon FET)
PMOS ( MOS saluran P) NMOS (MOS saluran N) Masih banyak lagi

26 FET VDS VGS ID IS FET Parameter FET : ID, VGS, VDS. Dasar pemikiran FET: Ada arus ID = IS yang mengalir melalui saluran, yang besarnya saluran dikendalikan oleh tegangan VGS. Karena arus lewat saluran (yang berupa hambatan) maka ada tegangan VDS.

27 Junction FETs

28 JFET saluran N

29 Daerah deplesi membesar dengan bertambahnya tegangan balik

30

31 Saluran N

32

33

34

35 Arus Drain current vs tegangan drain-ke-source
(tegangan gate-source = 0)

36 n-Channel FET for vGS = 0.

37 Typical drain characteristics of an n-channel JFET.

38 If vDG exceeds the breakdown voltage VB,
drain current increases rapidly.

39

40 KURVA KARAKTERISTIK Junction FET
Hubungan VGS dan ID k : konstanta VP : tegangan pinch-off atau threshold. Arus dibatasi hanya saat tegangan VGS = 0

41 Junction FET – Sumber Arus
RS VDD RLoad Kurva tak dipengaruhi tegangan VDS. Arus hanya dipengaruhi VGS bukan VDS. RS membuat VGS selalu negatip. Misalnya RS = 4K,  VGS = -4 V. Arus di Rload = 1 mA.

42 KURVA VDS-ID Junction FET
Ada dua daerah operasi : saturation linear. Linear Saturation Linear Saturation

43 JFET - variable resistor
VDS, DRAIN-SOURCE VOLTAGE, (Volts) VGS RG VDD RD For low values of VDS the slopes, change from a resistance (~5v/2.7mA~1.9k) to a resistance (5v/10mA~0.5k). A resistance is controlled by an input voltage. This makes it possible to have an element in a circuit that can be electronically adjusted.

44 JFET - variable resistor (2)
VGS RG VDD RD Now lets analyze the circuit. In the linear region we had a relationship between ID and VDS. To find the effective resistance this is the voltage across the channel divided by the current through the channel. If it wasn’t for the last term, we would have a value of 1/RDS that was proportional to VGS, the control voltage and didn’t depend on VDS (remember VT is a constant of the FET, the pinch off voltage). This is like a resistor, and it forms a VOLTAGE DIVIDER with RD.

45 n-Channel depletion MOSFET.

46 showing channel length L and channel width W.
n-Channel enhancement MOSFET showing channel length L and channel width W.

47 showing channel length L and channel width W.
n-Channel depletion MOSFET showing channel length L and channel width W.

48 enhancement-mode n-channel MOSFET

49 vGS < Vto  pn junction antara drain dan body  reverse biased  iD=0.

50 Terbentuk saluran N vGS < Vto  pn junction antara drain dan body  reverse biased  iD=0.

51 For vGS < Vto the pn junction between drain and body
is reverse biased and iD=0.

52 vGS >Vto  terbentuk saluran n. vGS bertambah  saluran membesar.
vDS kecil ,I D sebanding dengan vDS. resistor tergantung nilai vGS.

53 Laju pertambahan iD : melambat Saat vDS> vGS -Vto,  iD tetap
vDS bertambah, saluran mengecil di drain dan Laju pertambahan iD : melambat Saat vDS> vGS -Vto,  iD tetap

54 Threshold Voltage Vto (VP)

55 Kurva karakteristik transistor NMOS

56 Drain characteristics

57 Rangkaian penguat sederhana menggunakan NMOS .

58 Drain characteristics and load line

59 vDS versus time.

60

61 Graphical solution

62

63 The more nearly horizontal bias line results in less change in the Q-point.

64 Sinyal campuran

65 Rangkaian Ekivalen FET

66 Rangkaian ekivalen FET ( iD terpengaruh vDS)

67 Penentuan gm dan rd

68 Common-source amplifier.

69 Rangkaian Ekivalen Common-Source amplifier.

70 Common-source amplifier dengan nilai R

71 vo(t) dan vin(t) versus time

72 Gain magnitude versus frequency

73 Source follower.

74 Rangkaian Ekivalen Source Follower.

75 Common-gate amplifier.

76 n-Channel depletion MOSFET.

77 Drain current versus vGS in the saturation region
for n-channel devices.

78 p-Channel FET circuit symbols. Sama = n-channel devices,
kecuali arah panah

79 MOSFET-switch VDD RLOAD IRF510 RG
Power MOSFET dapat dialiri arus besar sampai 75 A, dan daya 150 W. Saat ON punya hambatan sekitar 10 Ohm. Contoh : IRF510 Mempunyai arus maksimum 5,6 A dab hambatan saat ON 0,4 Ohm. VGS

80 MOSFET-switch (2) Kurva ID vs. VGS. Ideal saklar: saat OFF  Arus =0.
Note the log scale! Kurva ID vs. VGS. Ideal saklar: saat OFF  Arus =0. Dari kuva terlihat : Tegangan VGS < 3 volt,  ID = 0 > 5 V  arus besar. ON OFF

81 PMOS P-MOS It is made in n-type silicon. gate source drain
In this device the gate controls hole flow from source to drain. It is made in n-type silicon. |VGS |>|Vt | source drain n-type Si p gate What if we apply a big negative voltage on the gate? If |VGS |>|Vt | (both negative) then we induce a + charge on the surface (holes)

82 NMOS and PMOS Compared NMOS “Body” – p-type Source – n-type
Drain – n-type VGS – positive VT – positive VDS – positive ID – positive (into drain) PMOS “Body” – n-type Source – p-type Drain – p-type VGS – negative VT – negative VDS – negative ID – negative (into drain) G G S D S D ID ID n p n p n B B ID 4 3 2 1 VDS VGS=3V 1 mA VGS=0 (for IDS = 1mA) 4 3 2 1 VDS VGS= 3V 1 mA VGS=0 ID (for IDS = -1mA)

83 CIRCUIT SYMBOLS G S D PMOS circuit symbol G S D NMOS circuit symbol A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS.

84 PMOS Transistor Switch Model
Operation compared to NMOS: It is complementary. G S D VDD Switch OPEN VDD G S D V=0 Switch CLOSED S D G VG =0 Switch is closed: Drain (D) is connected to Source (S) when VG =0 VG = VDD Switch is open : Drain (D) is disconnected from Source (S) when VG = VDD For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”)