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Diterbitkan olehAdi Falah Telah diubah "10 tahun yang lalu
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Organisasi Komputer Dosen Pembimbing : Muhammad Adri S
Organisasi Komputer Dosen Pembimbing : Muhammad Adri S.Pd,MT Handbook : Computer Organization and architecture th Edition – Prentice Hall by William Stalling Materi 3 Bus-Bus Sistem
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Konsep Program Sistem hardware tidak fleksibel
Tujuan umum hardware untuk melakukan tugas-tugas yang berbeda, dengan jalan memberikan koresksi sinyal kontrol Dengan mengubah hubungan (re-wiring),berarti memberikan set sinyal kontrol baru
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Apa itu program? Suatu urutan langkah-langkah kerja
Untuk tiap langkah, suatu operasi aritmatik atau logika dilakukan Untuk tiap operasi, dibutuhkan pengaturan sinyal kontrol yang berbeda
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Fungsi Unit Kontrol Biasanya setiap operasi mempunyai kode yang unik
Misal ADD, MOVE Suatu bagian hardware menerima kode dan mengirimkan sinyal kontrol We have a computer!
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Komponen - komponen Unit Kontrol dan ALU merupakan bagian yang terdapat dalam CPU (Central Processing Unit) Data and instruksi perlu dimasukkan ke dalam sistem untuk mendapatkan suatu keluaran Input/output Media penyimpanan sementara (temporary storage) kode and hasil proses diperlukan Memori utama
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Komponen Komputer : Top Level View
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Putaran instruksi Dua langkah: Fetch Execute
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Putaran Fetch Program Counter (PC) menyimpan alamat instruksi berikutnya untuk di fetch Prosessor mem-fetch-kan instruksi dari lokasi memori yang ditunjuk oleh PC Peningkatan PC Instruksi dikirim ke Instruction Register (IR) Prosessor menginterpretasikan instruksi dan melakukan aksi yang diperlukan
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Putaran Eksekusi Processor-memory Processor I/O Data processing
Data ditransfer antara CPU dan memori utama Processor I/O Data ditransfer antara CPU dan modul I/O Data processing Beberapa operasi aritmatik dan logika terhadap data Control Mengatur urutan-urutan operasi Misalnya jump Kombinasi proses di atas
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Contoh Eksekusi Program
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Putaran Instruksi - State Diagram
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Interupsi Mekanisme oleh modul-modul lainnya (mis. I/O) untuk mengubah urutan normal proses yang berlangsung Program Misal : overflow, division by zero Timer Dihasilkan oleh internal processor timer Digunakan dalam pre-emptive multi-tasking I/O Dari pengontrol I/O Hardware failure Misalnya bit paritas memori error
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Program Flow Control
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Lingkaran Interrupt Ditambahkan ke dalam putaran instruksi
Prosessor mencek adanya interrupt Diindikasikan oleh suatu interrupt signal Jika tidak ada interrupt, fetch instruksi berikutnya Jika interrupt ditunda: Sedang mengksekusi program Save context Seting PC untuk memulai alamat interrupt handler routine Proses interrupt Kembalikan context dan lanjtkan program yang di interrupt
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Putaran Instruction (dengan Interrupts) - State Diagram
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Multiple Interrupts Disable interrupts Define priorities
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt
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Multiple Interrupts - Sequential
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Multiple Interrupts - Nested
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Connecting All the units must be connected
Different type of connection for different type of unit Memory Input/Output CPU
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Memory Connection Receives and sends data
Receives addresses (of locations) Receives control signals Read Write Timing
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Input/Output Connection(1)
Similar to memory from computer’s viewpoint Output Receive data from computer Send data to peripheral Input Receive data from peripheral Send data to computer
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Input/Output Connection(2)
Receive control signals from computer Send control signals to peripherals e.g. spin disk Receive addresses from computer e.g. port number to identify peripheral Send interrupt signals (control)
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CPU Connection Reads instruction and data
Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts
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Buses There are a number of possible interconnection systems
Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)
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What is a Bus? A communication pathway connecting two or more devices
Usually broadcast Often grouped A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown
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Data Bus Carries data Width is a key determinant of performance
Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance 8, 16, 32, 64 bit
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Address bus Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system e.g has 16 bit address bus giving 64k address space
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Control Bus Control and timing information Memory read/write signal
Interrupt request Clock signals
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Bus Interconnection Scheme
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Big and Yellow? What do buses look like?
Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards e.g. PCI Sets of wires
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Single Bus Problems Lots of devices on one bus leads to:
Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems
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Traditional (ISA) (with cache)
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High Performance Bus
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Bus Types Dedicated Multiplexed Separate data & address lines
Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance
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Bus Arbitration More than one module controlling the bus
e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed
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Centralised Arbitration
Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate
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Distributed Arbitration
Each module may claim the bus Control logic on all modules
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Timing Co-ordination of events on bus Synchronous
Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event
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Synchronous Timing Diagram
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Asynchronous Timing Diagram
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PCI Bus Peripheral Component Interconnection
Intel released to public domain 32 or 64 bit 50 lines
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PCI Bus Lines (required)
Systems lines Including clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration Not shared Direct connection to PCI bus arbiter Error lines
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PCI Bus Lines (Optional)
Interrupt lines Not shared Cache support 64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan For testing procedures
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PCI Commands Transaction between initiator (master) and target
Master claims bus Determine type of transaction e.g. I/O read/write Address phase One or more data phases
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PCI Read Timing Diagram
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PCI Bus Arbitration
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Foreground Reading Stallings, chapter 3 (all of it)
In fact, read the whole site!
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