Pertemuan 12 Arithmetic Network di VLSI

Presentasi berjudul: "Pertemuan 12 Arithmetic Network di VLSI"— Transcript presentasi:

1 Pertemuan 12 Arithmetic Network di VLSI
Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01 Pertemuan 12 Arithmetic Network di VLSI

2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menerapkan gerbang logik, switching logik, dan atau struktur deskripsi Verilog untuk membangun rangkaian arithmetic sederhana dalam CMOS VLSI.

3 Bit Adder x s y c 1 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 HA
x y s c half adder Half Adder 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 operasi adder HA x y s c simbol x y s c rangkaian module half_adder_gate (sum, c_out, x, y) ; input x, y ; output sum, c_out ; and (c_out, x, y) ; xor (sum, x, y) ; endmodule Verilog HDL: 1

4 Bit Adder a + b: a = a3a2a1a0 b = b3b2b1b0 a3a2a1a0 Full Adder
c4 s3s2s1s0 a + b: Full Adder ci ai bi si ci+1 + FA (+) ai bi ci ci+1 si ai bi ci si ci+1 si = ai  bi  ci ci+1 = ai . bi + ci . (ai  bi)

5 Bit Adder Verilog HDL: ai bi Full Adder ai bi ci+1 ci ci+1 ci HA
si Full Adder ci+1 ci rangkaian si module full_adder_HA (sum, c_out, a, b, c_in) ; input a, b, c_in ; output sum, c_out ; wire wa, wb, wc ; half_adder_gate (wa, wb, a, b) ; half_adder_gate (sum, wc, wa, c_in) ; or (c_out, wb, wc) ; endmodule Verilog HDL:

6 Ripple Carry Adder + Verilog HDL: Adder a b s cn
4-bit ripple carry adder circuit + a2 b2 s2 a3 b3 s3 a0 b0 s0 a1 b1 s1 c0 c1 c2 c3 c4 module four_bit_adder (sum, c_4, a, b, c_0) ; input [3:0] a, b ; input c_0 ; output [3:0] sum ; output c_4 ; assign {c_4, sum} = a + b + c_0 ; endmodule Verilog HDL:

7 Carry Look Ahead Adder gi pi ai . bi ai  bi ai = bi = 0 ai = bi = 1
ci Ci+1 si gi pi ai . bi ai  bi ai = bi = 0 ai = bi = 1 ai  bi 1 Basic Carry Look Ahead Algorithm

8 Multiplier Dasar operasi: 0 x 0 = 0 0 x 1 = 0 1 x 0 = 0 1 x 1 = 1 Perkalian dilakuan dengan cara menuliskan kembali bilangan yang dikali jika bit bilangan pengalinya “1”, dengan penulisan LSB dari bilangan yang dikali ditulis dibawah bit “1” pengali bersangkutan. Kemudian hasil perkalian adalah penjumlahan penulisan kembali bilangan yang dikali tersebut. Contoh: 1 0 0 x x

9 Multiplier Register-based multiplier network n-bit adder MUX
multiplicand multiplier n shr  Product register (2n) Register-based multiplier network

10 Array Multiplier Multiplier Array p7 p6 p5 p4 p3 p2 p1 p0 P7 P6 P5 P4
b0 b1 b2 b3 a3 a2 a1 a0 Multiplier Array a2b0 a3b0 a0b0 a1b0 a2b1 a3b1 a0b1 a1b1 a2b2 a3b2 a0b2 a1b2 a2b3 a3b3 a0b3 a1b3 p7 p6 p5 p4 p3 p2 p1 p0

11 RESUME Bit Adder: Half Adder, Full Adder. Ripple Carry Adder. Carry Look ahead adder. Multiplier