1 Pertemuan 24 Reduced Instruction Set Computer 2 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1.

Presentasi berjudul: "1 Pertemuan 24 Reduced Instruction Set Computer 2 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1."— Transcript presentasi:

1 1 Pertemuan 24 Reduced Instruction Set Computer 2 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1

2 2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menjelaskan prinsip kerja Reduced Instruction Set Computer

3 3 Outline Materi Instruction Execution Characteristics The Use of Large Register File Compiler-Based Register Optimization Reduced Instruction Set Architecture RISC Pipelining RISC versus CISC Controversy

4 4 Reduced instruction set architecture Why CISC

5 5 Reduced instruction set architecture Code relative to RISC I [PATT82a][KATE83][HEAT84] 11 C Programs12 C Programs5 C Programs RISC I1.0 VAX-11/7800.80.67 M680000.9 Z80021.21.12 PDP-11/700.90.71

6 6 Reduced instruction set architecture Characteristics of Reduced Instruction Set Architectures 1.One instruction per cycle 2.Register to register operation 3.Simple addressing modes 4.Simple instruction formats

7 7 Reduced instruction set architecture Two comparisons of register to register and memory to memory approaches

8 8 Reduced instruction set architecture Design and layout effort for some microprocessor TransistorDesignLayout (thousands)(person months) RISC I441512 RISC II411812 M680006810070 Z8000186070 Intel iA Px-43211017090

9 9 RISC pipelined

10 10 Reduced instruction set architecture Optimization of pipelined Normal and delay branch AddressNormal branchDelay branchOptimized delay branch 100Load X, A 101Add 1, A Jump 105 102Jump 105Jump 106Add 1, A 103Add A, BNoopAdd A, B 104Sub C, BAdd A, BSub C, B 105Store A, ZSub C, BStore A, Z 106Store A, Z

11 11 Reduced instruction set architecture Optimization of pipelined