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Chapter 8: Memory Management. 8.2 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 8: Memory Management Background Swapping Contiguous.

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Presentasi berjudul: "Chapter 8: Memory Management. 8.2 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 8: Memory Management Background Swapping Contiguous."— Transcript presentasi:

1 Chapter 8: Memory Management

2 8.2 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Chapter 8: Memory Management Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging

3 8.3 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Background Program harus dibawa ke dalam memori dan ditempatkan dalam proses untuk dijalankan Input queue(Antrian masuk) – kumpulan proses pada disk yang menunggu untuk dibawa ke memori untuk menjalankan program Program user melalui beberapa langkah sebelum dijalankan

4 8.4 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Mapping Program Address Space to Memory Address Space

5 8.5 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Binding of Instructions and Data to Memory Compile time: Jika lokasi memori diketahui sejak awal, kode absolut dapat dibangkitkan, apabila terjadi perubahan alamat awal harus dilakukan kompilasi ulang. Misalnya : program format.com pada MS-DOS adalah kode absolut yang diikat pada saat waktu kompilasi Load time: Harus membangkitkan kode relokasi jika lokasi memori tidak diketahui pada saat waktu kompilasi. Execution time: Pengikatan ditunda sampai waktu eksekusi jika proses dapat dipindahkan selama eksekusi dari satu segmen memori ke segmen memori lain). Memerlukan dukungan perangkat keras untuk memetakan alamat (misalnya register basis dan limit). Alamat pengikatan dari instruksi dan data ke alamat memori dapat terjadi pada 3 tahap yang berbeda.

6 8.6 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Multistep Processing of a User Program

7 8.7 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Simple program Sss How to bind with physical address ?

8 8.8 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Binding Logical to Physical xxx

9 8.9 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Binding Logical to physical vvv

10 8.10 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Binding logical to physical vv

11 8.11 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Logical vs. Physical Address Space Alamat yang dibangkitkan oleh CPU disebut alamat logika (logical address) dimana alamat terlihat sebagai uni memory yang disebut alamat fisik (physical address). Tujuan utama manajemen memori adalah konsep meletakkan ruang alamat logika ke ruang alamat fisik. Logical address –Himpunan dari semua alamat logika yang dibangkitkan oleh program disebut dengan ruang alamat logika (logical address space) Physical address – himpunan dari semua alamat fisik yang berhubungan dengan alamat logika disebut dengan ruang alamat fisik (physical address space). Hasil skema waktu kompilasi dan waktu pengikatan alamat pada alamat logika dan alamat memori adalah sama. Tetapi hasil skema waktu pengikatan alamat waktu eksekusi berbeda. dalam hal ini, alamat logika disebut dengan alamat maya (virtual address).

12 8.12 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Memory-Management Unit ( MMU ) Hardware perangkat keras yang memetakan alamat virtual ke alamat fisik. Pada skema MMU, nilai register relokasi ditambahkan ke setiap alamat yang dibangkitkan oleh proses user pada waktu dikirim ke memori. Nilai dari register relokasi ditambahkan ke setiap alamat yang dibangkitkan oleh proses user pada waktu dikirim ke memori User program tidak pernah melihat alamat fisik secara real. Tujuannya untuk melakukan mapping physical address ke logical address dan sebaliknya.

13 8.13 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Dynamic relocation using a relocation register

14 8.14 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Dynamic Loading Untuk memperoleh utilitas ruang memori, dapat menggunakan dynamic loading. Dengan dynamic loading, sebuah rutin tidak disimpan di memori sampai dipanggil. Semua rutin disimpan pada disk dalam format relocatable load. Penggunaan memori ruang yang lebih baik; routine yang tidak digunakan maka tidak akan pernah diproses Sangat berguna ketika dibutuhkan kode dalam jumlah besar untuk menghandle kasus yang jarang terjadi Tidak ada dukungan khusus dari operating, diperlukan implementasi melalui rancangan program.

15 8.15 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Dynamic Linking Konsep dynamic linking sama dengan dynamic loading. Pada saat loading, linking ditunda sampai waktu eksekusi Terdapat kode kecil yang disebut stub digunakan untuk meletakkan rutin library di memori dengan tepat. Stub diisi dengan alamat rutin dan mengeksekusi rutin. biasanya digunakan dengan sistem library, seperti language subroutine library. Tanpa fasilitas ini, semua program pada sistem perlu mempunyai copy dari library language di dalam executable image Operating system dibutuhkan untuk mengecek jika routine berada dalam proses alamat memori. Ex. bila proses-proses di memori utama saling diproteksi, maka sistem operasi melakukan pengecekan apakah rutin yang diminta berada diluar ruang alamat. Beberapa proses diijinkan untuk mengakses memori pada alamat yang sama.

16 8.16 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Swapping Proses dapat ditukarkan sementara keluar dari memory backing store, dan kemudian dibawa kembali ke memory untuk melanjutkan eksekusi Backing store – disk besar dengan kecepatan tinggi yang cukup untuk meletakkan copy dari semua memory image untuk semua user, sistem juga harus menyediakan akses langsung ke memory image tersebut. Roll out, roll in – swapping varian digunakan untuk algoritma penjadwalan berbasis prioritas; proses yang prioritas lebih rendah ditukar sehingga proses yang prioritas tinggi dapat di load dan dieksekusi Kebijakan penukaran juga dapat digunakan pada algoritma penjadwalan berbasis prioritas. Jika proses mempunyai prioritas lebih tinggi datang dan meminta layanan, memori akan swap out proses dengan prioritas lebih rendah sehingga proses dengan prioritas lebih tinggi dapat di-load dan dieksekusi. Umumnya sebuah proses yang di-swap out akan menukar kembali ke ruang memori yang sama dengan sebelumnya.

17 8.17 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Schematic View of Swapping

18 8.18 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Contiguous Allocation Memori Utama biasanya dibagi menjadi partisi: Resident operating system, biasanya dilakukan di memori rendah dengan interrupt vector Pengguna proses kemudian dilakukan di memory tinggi Single -partition allocation Relocation-register scheme digunakan untuk memproteksi pengguna proses dari satu ke lainnya dan perubahan data dan kode operating system Relocation register terdiri dari alamat fisik terkecil; batas register berisi range dari logical addresses ; tiap logical address harus lebih rendah dari limit register

19 8.19 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts A base and a limit register define a logical address space

20 8.20 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts HW address protection with base and limit registers

21 8.21 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Contiguous Allocation (Cont.) Multiple-partition allocation Hole – block of available memory; holes of various size are scattered throughout memory When a process arrives, it is allocated memory from a hole large enough to accommodate it Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS process 5 process 8 process 2 OS process 5 process 2 OS process 5 process 2 OS process 5 process 9 process 2 process 9 process 10

22 8.22 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. How to satisfy a request of size n from a list of free holes First-fit and best-fit better than worst-fit in terms of speed and storage utilization

23 8.23 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block Compaction is possible only if relocation is dynamic, and is done at execution time I/O problem  Latch job in memory while it is involved in I/O  Do I/O only into OS buffers

24 8.24 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts External and Internal Fragmentation

25 8.25 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes) Divide logical memory into blocks of same size called pages. Keep track of all free frames To run a program of size n pages, need to find n free frames and load program Set up a page table to translate logical to physical addresses Internal fragmentation

26 8.26 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

27 8.27 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Address Translation Architecture

28 8.28 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Paging Example

29 8.29 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Paging Example

30 8.30 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Implementation of Page Table Page table is kept in main memory Page-table base register (PTBR) points to the page table -> p Page-table length register (PRLR) indicates size of the page table ->d In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

31 8.31 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Associative Memory Associative memory – parallel search Address translation (A´, A´´) If A´ is in associative register, get frame # out Otherwise get frame # from page table in memory Page #Frame #

32 8.32 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Paging Hardware With TLB

33 8.33 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Effective Access Time Associative Lookup =  time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers; ration related to number of associative registers Hit ratio =  Effective Access Time (EAT) EAT = (1 +  )  + (2 +  )(1 –  ) = 2 +  – 

34 8.34 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page “invalid” indicates that the page is not in the process’ logical address space

35 8.35 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Valid (v) or Invalid (i) Bit In A Page Table

36 8.36 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Page Table Structure Hierarchical Paging Hashed Page Tables Inverted Page Tables

37 8.37 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Hierarchical Page Tables Break up the logical address space into multiple page tables A simple technique is a two-level page table

38 8.38 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into: a 10-bit page number a 10-bit page offset Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page number page offset pipi p2p2 d 10 12

39 8.39 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Two-Level Page-Table Scheme

40 8.40 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture

41 8.41 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Hashed Page Tables Common in address spaces > 32 bits The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

42 8.42 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Hashed Page Table

43 8.43 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Inverted Page Table One entry for each real page of memory Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one — or at most a few — page-table entries

44 8.44 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Inverted Page Table Architecture

45 8.45 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes Private code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space

46 8.46 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Shared Pages Example

47 8.47 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation Memory-management scheme that supports user view of memory A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

48 8.48 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts User’s View of a Program

49 8.49 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Logical View of Segmentation user spacephysical memory space

50 8.50 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation Architecture Logical address consists of a two tuple:, Segment table – maps two-dimensional physical addresses; each table entry has: base – contains the starting physical address where the segments reside in memory limit – specifies the length of the segment Segment-table base register (STBR) points to the segment table’s location in memory Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR

51 8.51 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation Architecture (Cont.) Relocation. dynamic by segment table Sharing. shared segments same segment number Allocation. first fit/best fit external fragmentation

52 8.52 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation Architecture (Cont.) Protection. With each entry in segment table associate: validation bit = 0  illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level Since segments vary in length, memory allocation is a dynamic storage-allocation problem A segmentation example is shown in the following diagram

53 8.53 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Address Translation Architecture

54 8.54 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Example of Segmentation

55 8.55 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Sharing of Segments

56 8.56 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation with Paging – MULTICS The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment, but rather the base address of a page table for this segment

57 8.57 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts MULTICS Address Translation Scheme

58 8.58 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Segmentation with Paging – Intel 386 As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme

59 8.59 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Intel Address Translation

60 8.60 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Linux on Intel 80x86 Uses minimal segmentation to keep memory management implementation more portable Uses 6 segments: Kernel code Kernel data User code (shared by all user processes, using logical addresses) User data (likewise shared) Task-state (per-process hardware context) LDT Uses 2 protection levels: Kernel mode User mode

61 End of Chapter 8

62 8.62 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts ml ml link.doc

63 8.63 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Free Frames Before allocation After allocation

64 8.64 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts 11/02/best-fit-first-fit-and-worst-fit- memory.html

65 8.65 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Best Fit

66 8.66 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts First Fit

67 8.67 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts Worst Fit


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