1 Pertemuan 18 Control Unit 1 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1.

Presentasi berjudul: "1 Pertemuan 18 Control Unit 1 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1."— Transcript presentasi:

1 1 Pertemuan 18 Control Unit 1 Matakuliah: H0344/Organisasi dan Arsitektur Komputer Tahun: 2005 Versi: 1/1

2 2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menjelaskan prinsip kerja control unit dalam mengeksekusi beberapa instruction

3 3 Outline Materi Micro-Operations Control of Processor Hardwired Implementation

4 4 Micro-operation Constituent elements of a program execution

5 5 Micro-operation The fetch cycle t1 : MAR  PC t2 :MBR  Memory PC  PC + 1 t3 : IR  MBR

6 6 Micro-operation The indirect cycle t1 : MAR  IR(address) t2 :MBR  Memory t3 : IR(address)  MBR(address) The interrupt cycle t1 : MBR  PC t2 :MAR  Save_address PC  Routine_address t3 : Memory  MBR

7 7 The execute cycle t1 : MAR  IR(address) t2 :MBR  Memory t3 : R1  R1 + MBR Micro-operation t1 : MAR  IR(address) t2 :MBR  Memory t3 : MBR  MBR + 1 t4 :Memory  MBR If (MBR = 0) then (PC  PC + 1) t1 : MAR  IR(address) MBR  PC t2 : PC  IR(address) Memory  MBR t3 : PC  PC + 1 Add R1, X Isz X Bsa X

8 8 Micro-operation Flowchart for instruction cycle

9 9 Model of the control unit Control of The processor

10 10 Data paths and control signals Control of The processor

11 11 Micro-operations and control signals Control of The processor Micro-operationTimingActive Control Signals Fetcht1 : MAR  PC t2 : MBR  Memory PC  PC + 1 t3 : IR  MBR C2 C5, CR C4 Indirectt1 : MAR  IR(address) t2 : MBR  Memory t3 : IR(address)  MBR (address) C8 C5 C4 Interruptt1 : MAR  PC t2 : MBR  Save address PC  Routine address t3 : Memory  MBR C2 C12, CW

12 12 Internal Processor Organization Control of the processor

13 13 Hardwired implementation