Presentasi berjudul: "IKI10230 Pengantar Organisasi Komputer Bab 5.1: Memori"— Transcript presentasi:
1 IKI10230 Pengantar Organisasi Komputer Bab 5.1: Memori Sumber: 1. Hamacher. Computer Organization, ed Materi kuliah CS152/1997, UCB.9 April 2003Bobby Nazief Qonita Shahabbahan kuliah:
2 Memori: Tempat Penyimpanan Data Keyboard, MouseComputerProcessor(active)Memory(passive)(whereprograms,datalive whenrunning)DevicesInputControl(“brain”)Disk (permanent storages)Datapath(“brawn”)OutputThat is, any computer, no matter how primitive or advance, can be divided into five parts:1. The input devices bring the data from the outside world into the computer.2. These data are kept in the computer’s memory until ...3. The datapath request and process them.4. The operation of the datapath is controlled by the computer’s controller.All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.5. Getting the data back to the outside world is the job of the output devices.The most COMMON way to connect these 5 components together is to use a network of busses.Display, Printer
3 Istilah/Jenis Semikonduktor Memori RAM --Random Access Memory time taken to access any arbitrary locationin memory is constantSRAM --Static RAM A RAM chip design technology (see later)DRAM --Dynamic RAM A RAM chip design technology (see later)ROM --Read Only Memory ROMs are RAMs with data built-in when thechip is created. Usually stores BIOS info.Older uses included storage of bootstrap infoPROM --Programmable ROM A ROM which can be programmedEPROM --Erasable PROM A PROM which can be programmed, erasedby exposure to UV radiationEEROM – Electrical EPROM A PROM programmed & erased electrically
4 Masih tentang Istilah … Tambahan istilah:SIMM Single In-Line Memory ModuleA packaging technology (single 32-bit data path)DIMM Dual In-Line Memory ModuleA packaging technology (dual 32-bit data paths)FPM RAM Fast Page-Mode RAMAn older technology capable of about 60ns cycle timeEDO RAM Extended-data-out RAMMore modern FPM RAM, exploiting address coherency (see cache`later) capable of about 20ns access speedSDRAM Synchronous DRAMSynchronous Dynamic RAM; allows access speeds aslow as about 10nsPC 100, PC133, PC2100, PC2600 => memory product you can buy
5 Connection: Memory - Processor k-bit address busMemorySampai 2k addressablelocationsMARn-bit data busPanjang word= n bitsMDRControl lines,R/W, MFC, etc.
6 Konsep Dasar Memory: akses per byte Transfer dilakukan per-word (cepat, kelipatan bytes)Misalkan: 32-bit komputer => address 32 bit Kemampuan addressing: 2 ^ 32 = 4 GbytesJika transfer data per-word: 32 bit (data bus) => 4 bytesBytes mana yang diakses dari kemungkinan word tsb?Perlu 2 bits untuk menentukan bytes yang mana dari wordSisa bit: 30 bits digunakan untuk address word
7 Organisasi Internal Memori Bentuk array: terdiri dari sel memoriSel berisi 1 bit informasiBaris dari sel membentuk untaian satu wordContoh: 16 x 8 memorimemori SRAM mengandung 16 wordssetiap words terdiri dari 8 bit dataKapasitas memori: 16 x 8 = 128 bitsDecoder digunakan untuk memilih baris word mana yang akan diaksesTipikal SRAM, array 1 dimensi => indeks dari baris pada array tersebut.
8 Review: Static RAM Cell 6-Transistor SRAM CellLatch menyimpan state 1 bitTransistor T bertindak sebagai switchContoh: state 1Latch dapat berubah dengan:put bit value pada b dan b’word line pull high (select)word(row select)1TT1b’bWrite:1. Drive bit lines sesuai dengan bit (mis. b = 1, b’ = 0)2. Select row store nilai b dan b’ menjadi state latchRead:Precharge (set) bit lines highSelect row3. Sense amp mendeteksi bit lines mana yang low state bitThe classical SRAM cell looks like this. It consists of two back-to-back inverters that serves as a flip-flop. Here is an expanded view of this cell, you can see it consists of 6 transistors.In order to write a value into this cell, you need to drive from both sides. For example, if you want to write a 1, you will drive “bit” to 1 while at the same time, drive “bit bar” to zero.Once the bit lines are driven to their desired values, you will turn on these two transistors by setting the word line to high so the values on the bit lines will be written into the cell.Remember now these are very very tiny transistors so we cannot rely on them to drive these long bit lines effectively during read.Also, the pull down devices are usually much stronger than the pull up devices. So the first thing we need to do on read is to charge these two bit lines to a high values.Once these bit lines are charged to high, we will turn on these two transistors so one of these inverters (the lower one in our example) will start pulling one of the bit line low while the other bit line will remain at HI.It will take this small inverter a long time to drive this long bit line to low but we don’t have to wait that long since all we need to detect the difference between these two bit lines.And if you ask any circuit designer, they will tell you it is much easier to detect a “differential signal” (point to bit and bit bar) than to detect an absolute signal.+2 = 30 min. (Y:10)
9 Organisasi Memori: 1-level-decode SRAM (128 x 8) Word 8 bit datab7b7’b1b1’b0b0’AddressdecoderW0A0W1A1memorycellsA6W127128 wordssense/writeampssense/writeampssense/writeampsR/W’CSInput/output linesd7d1d0
10 Organisasi Memori: 2-level-decode SRAM (1 K x 1) W05-bit decoderW132 x 32Memory cell arrayW31A05-bit row addressA1Sense/write circuitryA732 x 1Output/input multiplexerR/WCSA8A95-bit column address10-bit addressData Input/Output (1 bit)
11 Static RAM (SRAM)SRAM dapat menyimpan “state” (isi RAM) selama terdapat “tegangan” power supplySangat cepat, 10 nano-detikDensitas rendah (bits per chip) memerlukan 6 transistor per-sel mahalPilihan teknologi untuk memori yang sangat cepat dengan kapasitas kecil cache
12 Review: 1-Transistor Memory Cell (DRAM) Kapasitor menyimpan state 1 (charged) atau 0 (discharge)Perlu refresh!row selectWrite:1. Drive bit line2. Select row (T sebagai switch)Read:1. Select row2. Sense Amp (terhubung dengan bit line): sense & drives sesuai dengan value (threshold)3. Write: restore the value (high or low)RefreshJust do a dummy read to every cell.TCbitThe state of the art DRAM cell only has one transistor. The bit is stored in a tiny transistor.The write operation is very simple. Just drive the bit line and select the row by turning on this pass transistor.For read, we will need to precharge this bit line to high and then turn on the pass transistor.This will cause a small voltage change on the bit line and a very sensitive amplifier will be used to measure this small voltage change with respect to a reference bit line.Once again, the value we stored will be destroyed by the read operation so an automatic write back has to be performed at the end of every read.+ 2 = 48 min. (Y:28)
13 Classical DRAM Organization (square) bit (data) linesrowdecEach intersection representsa 1-T DRAM CellRAM CellArrayword (row) selectSimilar to SRAM, DRAM is organized into rows and columns.But unlike SRAM, which allows you to read an entire row out at a time at a word, classical DRAM only allows you read out one-bit at time time.The reason for this is to save power as well as area. Remember now the DRAM cell is very small we have a lot of them across horizontally.So it will be very difficult to build a Sense Amplifier for each column due to the area constraint not to mention having a sense amplifier per column will consume a lot of power.You select the bit you want to read or write by supplying a Row and then a Column address.Similar to SRAM, each row control line is referred to as the word line and each vertical data line is referred to as the bit line.+2 = 57 min. (Y:37)Column Selector &I/O CircuitsrowaddressColumnAddressRow and Column Address together:Select 1 bit a timedata
14 Densitas tinggi: 1 transistor/bit Dynamic RAM (DRAM)Slower than SRAMaccess time ~60 ns (paling cepat: 35 ns)Nonpersistantevery row must be accessed every ~1 ms (refreshed)Densitas tinggi: 1 transistor/bitLebih murah dari SRAM~$1/MByte Fragileelectrical noise, light, radiationPilihan teknologi memori untuk kapasitas besar dan “low cost” main memory
15 Organisasi DRAM 2-level (64Kx1) RAS’256 RowsRowdecoder256x256cell arrayRowaddresslatch\8row256 ColumnsA15-A8/A7-A0columnsense/writeampsCSR/W’colColumnaddresslatchcolumndecoder\8CAS’DoutDin
16 Rewrite/Refreshed (~30ns) Operasi DRAMRow Address (~50ns)Set Row address pada address lines & strobe RASSeluruh row dibaca & disimpan di column latchesIsi dari row memori cells akan di-refreshColumn Address (~10ns)Set Column address pada address lines & strobe CASAccess selected bitREAD: transfer from selected column latch to DoutWRITE: Set selected column latch to DinRewrite/Refreshed (~30ns)Write back entire row
17 DRAM Write Timing RAS’ CAS’ R/W’ A 256K x 8 DRAM D DRAM WR Cycle Time 98DRAM WR Cycle TimeRAS’CAS’ARow AddressCol AddressJunkRow AddressCol AddressJunkLet me show you an example. Here we are performing two write operation to the DRAM.Setup/hold times in colar barsRemember, this is very important. All DRAM access start with the assertion of the RAS line.When the RAS_L line go low, the address lines are latched in as row address. This is followed by the CAS_L line going low to latch in the column address.Of course, there will be certain setup and hold time requirements for the address as well as data as highlighted here.Since the Write Enable line is already asserted before CAS is asserted, write will occur shortly after the column address is latched in. This is referred to as the Early Write Cycle.This is different from the 2nd example I showed here where the Write Enable signal comes AFTER the assertion of CAS. This is referred to as a Later Write cycle.Notice that in the early write cycle, the width of the CAS line, which you as a logic designer can and should control, must be as long as the memory’s write access time.On the other hand, in the later write cycle, the width of the Write Enable pulse must be as wide as the WR Access Time.Also notice that the RAS line has to remain asserted (low) during the entire access cycle.The DRAM write cycle time is defined as the time between the two RAS pulse and is much longer than the DRAM write access time.+3 = 63 min. (Y:43)R/W’DJunkData InJunkData InJunkWR Access TimeWR Access Time
18 DRAM Read Timing RAS’ CAS’ R/W’ A 256K x 8 DRAM D DRAM Read Cycle Time 98DRAM Read Cycle TimeRAS’CAS’ARow AddressCol AddressJunkRow AddressCol AddressJunkSimilar to DRAM write, DRAM read can also be a Early read or a Late read.In the Early Read Cycle, Output Enable is asserted before CAS is asserted so the data lines will contain valid data one Read access time after the CAS line has gone low.In the Late Read cycle, Output Enable is asserted after CAS is asserted so the data will not be available on the data lines until one read access time after OE is asserted.Once again, notice that the RAS line has to remain asserted during the entire time. The DRAM read cycle time is defined as the time between the two RAS pulse.Notice that the DRAM read cycle time is much longer than the read access time.Q: RAS & CAS at same time? Yes, both must be low+2 = 65 min. (Y:45)R/W’DHigh ZJunkData OutHigh ZData OutRead AccessTimeRead AccessTime
19 Must Refresh Periodically DRAM: KinerjaTimingAccess time = 60ns < cycle time = 90nsNeed to rewrite rowModel asinkron: operasi memori dilakukan oleh controller circuit delay prosesor menunggu sampai cycle time selesai lalu melakukan request lagi.Must Refresh PeriodicallyPerform complete memory cycle for each rowApprox. every 1msHandled in background by memory controller
20 Perkembangan Teknologi Memori DRAM Teknologi memori: segi kecepatan akses berkembang sangat lambatGap yang semakin membesar dengan kecepatan prosesor (cycle sangat kecil => 1 nsec, akses memori orde puluhan nsec).Perkembangan teknologi DRAMBasis tetap sama: 1-transistor memori cell (menggunakan kapasitor)Inovasi dilakukan dari segi: cara melakukan aksesmemotong waktu akses (mis. CAS tidak diperlukan)burst mode: sekaligus mengambil data sebanyak mungkin (seluruh word)perlu tambahan rangkaian: register, latch dll
21 Enhanced Performance DRAMs Conventional AccessRow + ColRAS CAS RAS CAS ...Page ModeRow + Series of columnsRAS CAS CAS CAS ...Gives successive bitsVideo RAMShift out entire row sequentiallyAt video rateRowaddresslatchColumndecoder256x256cell arraysense/writeampscolumn& latchA15-A8/A7-A0\8R/W’CASRASrowcolEntire row buffered hereTypical Performancerow access time col access time cycle time page mode cycle time50ns ns 90ns ns
22 Fast Page Mode Operation ColumnAddressFast Page Mode DRAMN x M “SRAM” to save a rowAfter a row is read into the registerOnly CAS is needed to access other M-bit blocks on that rowRAS’ remains asserted while CAS’ is toggledN colsDRAMRowAddressN rowsN x M “SRAM”M bitsM-bit OutputSo with this register in place, all we need to do is assert the RAS to latch in the row address, then entire row is read out and save into this register.After that, you only need to provide the column address and assert the CAS needs to access other M-bit within this same row.I like to point out that even I use the word “SRAM” here but this is no ordinary sram. It has to be very small but the good thing is that it is internal to the DRAM and does not have to drive any external load.Anyway, this type of operation where RAS remains asserted while CAS is toggled to bring in a new column address is called Page Mode operation.Strore orw so don’t have to repeat: SRAMIt will become clearer why this is called Page Mode operation when we look into the operation of the SPARCstation 20 memory system.+ 2 = 71 min. (Y:51)1st M-bit Access2nd M-bit3rd M-bit4th M-bitRAS’CAS’ARow AddressCol AddressCol AddressCol AddressCol Address
23 SDRAM & DDR SDRAM SDRAM: Synchronous DRAM Address & Data are buffered in registersBurst Mode:Read/Write of different data lengths CAS signals are provided internallyStandards: PC100, PC133DDR SDRAM: Double-Data-Rate SDRAMData is transferred on both edges of the clockCell array is organized in 2 banks allows interleaving of word’s accessStandards: PC2100, PC2300RDRAM: Rambus DRAMHigh transfer rate using differential signalingMemory cells are organized in multiple banksStandards: proprietary owned by Rambus Inc.
24 SDRAM Operation Memory Latency: Memory Bandwidth: RAS’CAS’AddrRowColDataD0D1D2D3So with this register in place, all we need to do is assert the RAS to latch in the row address, then entire row is read out and save into this register.After that, you only need to provide the column address and assert the CAS needs to access other M-bit within this same row.I like to point out that even I use the word “SRAM” here but this is no ordinary sram. It has to be very small but the good thing is that it is internal to the DRAM and does not have to drive any external load.Anyway, this type of operation where RAS remains asserted while CAS is toggled to bring in a new column address is called Page Mode operation.Strore orw so don’t have to repeat: SRAMIt will become clearer why this is called Page Mode operation when we look into the operation of the SPARCstation 20 memory system.+ 2 = 71 min. (Y:51)Memory Latency:Waktu yang dibutuhkan untuk mentransfer word pertamaMemory Bandwidth:Jumlah word (byte/bit) yang dapat ditransfer per satuan waktu
25 Struktur Memori Besar (1/4) Misalkan: Chip memori 128K x 88 data lines17 address linesCS’Chips selectWE’CS’ WE’ Function Data LinesH X not selected Hi-ZL H Read data at location on address linesL L Write write data on data lines to addresson address lines
26 Contoh: Struktur 1 MB (2/4) 1 MB dapat dikonstruksi dengan organisasi 8 chips memori 128 KB (8 x 128 x 8 = 1 MB)The address space ispartitioned into 128Kblocks;block 0 has addresses K -1block 1 has addresses 128K K-1block 2 has addresses 256K K -1:block 7 has addresses 896K K -1This will be chip 0This will be chip 1This will be chip 7Berapa banyak bits yang diperlukan untuk alamat pada chips?memilih chips yang mana?
27 Contoh: Pembagian field address (3/4) 1MB membutuhkan alamat sebesar 20 bit,Ide: membagi field address menjadi 2 yakni: bits untuk memilih chips dan address pada field tsb.Bits (3 address bits)Bits (17 address bits)17 bits select the address in each128KB block (== each chip)3 address bits select on of the 8128KB blocks (chips)
29 Read-Only Memory ROM PROM EPROM EEPROM Flash Write once, by manufacturerPROMWrite once, by userEPROMErasable PROM (by exposing it to ultraviolet light)EEPROMElectrically, Erasable PROMFlash~EEPROMWrite in blocksLow power consumption battery drivenImplementation:Flash CardsFlash Drives:Better than disk (no movable parts faster response)
30 Ringkasan (.. To remember) DRAM lambat tapi murah dan kapasitas besar (densitas tinggi)Pilihan untuk memberikan kapasitas BESAR pada sistem memori.SRAM cepat tapi mahal dan kapasitas kecilPilihan untuk menyediakan sistem memori yang waktu aksesnya CEPAT.Struktur memori besar dapat dibangun dari kumpulan chips memori kecil:Field alamat dibagi: field address dan field untuk memilih chips/memori yang mana.Next topic: Trend teknologi memori (go to: http//www.tomshardware.com, search SDRAM guide)
31 Trend Teknologi Memori (DRAM) CPU-DRAM GapµProc60%/yr.DRAM7%/yr.110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000CPU1982Processor-MemoryPerformance Gap: (grows 50% / year)Performance“Moore’s Law”Y-axis is performanceX-axis is timeLatencyCliché:Not e that x86 didn’t have cache on chip until 1989Prosesor sangat cepat tidak efektif => kendala “bottleneck” berada pada sumber/tujuan data yakni memori.