Transistors (MOSFETs) MOS Field-Effect Transistors (MOSFETs) 1

sedr42021_0401a.jpg Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm. Microelectronic Circuits - Fifth Edition Sedra/Smith

Ingat pada p-n junction sedr42021_0402.jpg Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0403.jpg Figure 4.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS – Vt’ and thus iD is proportional to (vGS – Vt) vDS. Note that the depletion region is not shown (for simplicity). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0404.jpg Figure 4.4 The iD–vDS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistor whose value is controlled by vGS. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0405.jpg Figure 4.5 Operation of the enhancement NMOS transistor as vDS is increased. The induced channel acquires a tapered shape, and its resistance increases as vDS is increased. Here, vGS is kept constant at a value > Vt. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0406.jpg Figure 4.6 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS > Vt. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0407.jpg Figure 4.7 Increasing vDS causes the channel to acquire a tapered shape. Eventually, as vDS reaches vGS – Vt’ the channel is pinched off at the drain end. Increasing vDS above vGS – Vt has little effect (theoretically, no effect) on the channel’s shape. Microelectronic Circuits - Fifth Edition Sedra/Smith

Equipotential pada arah y (melebar) Kapasitansi gate-channel (dielektrik SiO2) per satuan area (1) (2) Muatan tersimpan dalam Kapasitor (3) sedr42021_0408.jpg Muatan tersimpan dalam “potongan” equipotensial (4) Figure 4.8 Derivation of the iD–vDS characteristic of the NMOS transistor. Microelectronic Circuits - Fifth Edition Sedra/Smith

Muatan pada celah potongan sehingga Medan listrik pada “potongan” Laju elektron (drift) Karena medan listrik sedr42021_0408.jpg Arus drift pada celah “potongan” Figure 4.8 Derivation of the iD–vDS characteristic of the NMOS transistor. Microelectronic Circuits - Fifth Edition Sedra/Smith

Arus drain yang disebabkan arus drift pada celah “potongan” dapat disusun menjadi Integrasi dengan batas source dan drain atau x antar 0 dan L dan tegangan 0 dan vDS sedr42021_0408.jpg memberikan Untuk saturasi arus drain menjadi Microelectronic Circuits - Fifth Edition Sedra/Smith

definisi konstanta sedr42021_0408.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0409.jpg Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device. Microelectronic Circuits - Fifth Edition Sedra/Smith

Potongan melintang Layout sedr42021_0409.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

arah panah menunjukkan arah junction seperti pada dioda Perhatikan: arah panah menunjukkan arah junction seperti pada dioda Kanal tipe n dan bodi tipe p sedr42021_0410a.jpg Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant. Microelectronic Circuits - Fifth Edition Sedra/Smith

Perilaku arus-tegangan MOSFET dan Daerah Operasinya Pengukuran/ Karakterisasi sedr42021_0411a.jpg Figure 4.11 (a) An n-channel enhancement-type MOSFET with vGS and vDS applied and with the normal directions of current flow indicated. (b) The iD–vDS characteristics for a device with k’n (W/L) = 1.0 mA/V2. Microelectronic Circuits - Fifth Edition Sedra/Smith

Daerah Trioda Syarat “Bentuk” Kanal 1. kanal terbentuk 2. Kanal kontinyu “Bentuk” Kanal Kanal kontinyu atau tegangan gate-drain masih membentuk kanal (daerah deplesi belum terlalu besar sehingga membuat kanal Pinch-off) sedr42021_0411a.jpg Persamaan arus-tegangan atau Microelectronic Circuits - Fifth Edition Sedra/Smith

Daerah Trioda Persamaan arus-tegangan untuk menjadi dapat dinyatakan sebagai sedr42021_0411a.jpg Dengan definisi menjadi Mengapa DS huruf kapital? syarat Microelectronic Circuits - Fifth Edition Sedra/Smith

Daerah Saturasi Syarat “Bentuk” Kanal 1. kanal terbentuk 2. Pinch-off Kanal pinch-off, tegangan gate-drain tidak lagi membentuk kanal, arus drain hanya ditentukan jumlah muatan yang dibentuk tegangan gate pada kanal sedr42021_0411a.jpg Persamaan arus-tegangan atau Microelectronic Circuits - Fifth Edition Sedra/Smith

Daerah Saturasi Persamaan arus-tegangan Untuk drain-gate terhubung singkat MOSFET selalu saturasi karena sedr42021_0412.jpg Figure 4.12 The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, k’n W/L = 1.0 mA/V2). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0413.jpg Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0414.jpg Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

dan dapat dinyatakan dengan sehingga Setelah mencapai saturasi apabila tegangan drain-source masih dinaikkan, maka panjang kanal berkurang Persamaan arus semula menjadi disusun ulang untuk dapat didekati dengan sebanding dengan sedr42021_0415.jpg dan dapat dinyatakan dengan sehingga Figure 4.15 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). Microelectronic Circuits - Fifth Edition Sedra/Smith

untuk maka ID Definisikan maka sehingga atau dimana sedr42021_0416.jpg Figure 4.16 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0417.jpg Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (4.22). Microelectronic Circuits - Fifth Edition Sedra/Smith

Daerah Trioda Daerah Saturasi Syarat Syarat 1. kanal terbentuk 2. Kanal kontinyu Persamaan arus-tegangan dengan Daerah Saturasi Syarat 1. kanal terbentuk 2. Pinch-off sedr42021_0418a.jpg Persamaan arus-tegangan Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that vGS and vDS are negative and iD flows out of the drain terminal. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0419.jpg Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region. Microelectronic Circuits - Fifth Edition Sedra/Smith

(a) Syarat (b) Syarat (c) Syarat Vt=-1V, kp’=60mA/V2, W/L=10, hitung VG agar FET konduksi VD untuk triode VD untuk saturasi untuk l=0, |VOV|, VG dan VD untuk ID=75mA ro untuk l=-0,02V-1 dan |VOV| dari (d) ID untuk l=-0,02V-1 dan |VOV| dari (d) pada VD=+3V dan VD=0V, lalu hitung ro dan bandingkan dengan (e) (a) Syarat sedr42021_e0408.jpg (b) Syarat (c) Syarat Figure E4.8 Microelectronic Circuits - Fifth Edition Sedra/Smith

(d) Asumsi saturasi (e) (f) Untuk ini sama! sedr42021_e0408.jpg Figure E4.8 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_tb0401a.jpg Table 4.1 Microelectronic Circuits - Fifth Edition Sedra/Smith

Body Effect pada tegangan threshold sedr42021_tb0401a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

ID diinginkan 400mA, VD =0,5V, RD dan RS? Vt=0,7V, mnCox=100mA/V2, L=1mm, dan W=32mm Langkah: 1. Cek konduksi? Cek saturasi atau triode? 2. Hitung VOV 3. Hitung VGS 4. Hitung VS sedr42021_0420.jpg Figure 4.20 Circuit for Example 4.2. Microelectronic Circuits - Fifth Edition Sedra/Smith

Vt=0,6V, mnCox=200mA/V2, L=0,8mm, dan W=4mm ID diinginkan 80mA, R? Vt=0,6V, mnCox=200mA/V2, L=0,8mm, dan W=4mm MOSFET dalam keadaan saturasi (mengapa?) sedr42021_0421.jpg Figure 4.21 Circuit for Example 4.3. Microelectronic Circuits - Fifth Edition Sedra/Smith

Rangkaian pada cabang kanan idem rangkaian sebelumnya, berapa arus pada R=20kW? Berapa tegangan drain? FET Q2 dan Q1 identik Anggap saturasi, VOV pada kedua rangkaian sama, maka arus sama, yaitu 80mA Tegangan VDS=VD>VOV maka FET Q2 dalam keadaan saturasi (anggapan benar) sedr42021_e0412.jpg Figure E4.12 Microelectronic Circuits - Fifth Edition Sedra/Smith

Rancang agar VD = 0,1V (atau RD?) Vt=1V, kn’W/L=1mA/V2 FET dalam keadaan trioda, karena sehingga sedr42021_0422.jpg Mengikuti nilai resistor baku yang tersedia untuk Toleransi 5% dapat digunakan 12kW Figure 4.22 Circuit for Example 4.4. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0423a.jpg Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0424.jpg Figure 4.24 Circuit for Example 4.6. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0425a.jpg Figure 4.25 Circuits for Example 4.7. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_e0416.jpg Figure E4.16 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0426a.jpg Fungsi R? Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0426c.jpg Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0427.jpg Figure 4.27 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the triode region and might not allow for sufficient negative signal swing. Microelectronic Circuits - Fifth Edition Sedra/Smith

MOSFET saturasi sedr42021_0427.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

MOSFET triode atau dengan untuk maka sedr42021_0427.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh Numerik kn’(W/L)=1mA/V2 Vt=1V VDD=10V RD=18kW Letak X Letak A Letak B sedr42021_0427.jpg Letak C Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh Numerik 10V Letak Q Q dapat dipilih tepat diantara jangkauan tegangan output atau 5,5V namun untuk mendapat gain yang lebih besar dipilih pada tegangan output 4V 5,5V 4V 2V sedr42021_0427.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh Numerik Tegangan input sedr42021_0428a.jpg Figure 4.28 Example 4.8. Microelectronic Circuits - Fifth Edition Sedra/Smith

1,741 0,275 5,05 1,816 0,333 4,00 1,891 0,397 2,85 sedr42021_0428b.jpg Figure 4.28 (Continued) Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh dengan SPICE Rangkaian Amplifier Sederhana dengan MOSFET Example 4.8 * * Rangkaiannya * FETnya FET drain gate source body nama_model M1 out in 0 0 NMOS1 L=1u W=1u * Resistor drain RD=18k R1 vdd out 18k * Power Supply VDD=10V VDD vdd 0 10 * Tegangan Input Sinusoidal DC 1.816V Amplitude AC 77mV Frekuensi 10KHz * Alternatif untuk sinyal seperti dalam teks menggunakan PWL *VS in 0 SIN(1.816 0.075 10k 0 0) VS in 0 PWL(0 1.816 50us 1.741 150us 1.891 250us 1.741 350us 1.891 450us 1.741 500us 1.816) .MODEL NMOS1 NMOS KP=1e-3 VTO=1 .end .control tran 5us 0.5ms plot in out plot out vs in sedr42021_0428b.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh dengan SPICE sedr42021_0428b.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Pemberian Bias Penguat MOSFET Cara paling “sederhana” dengan memberikan tegangan tetap (DC) langsung antara terminal gate dan source VGS Cara ini kurang tepat mengingat mobilitas pembawa muatan dan tegangan threshold fungsi (kuat) temperatur sehingga dapat memberikan arus drain yang berbeda pula seperti ditunjukkan pda kurva ini sedr42021_0429.jpg Figure 4.29 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among units of the same type. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0430a.jpg Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation using two supplies. Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh kn’(W/L)=1mA/V2 Vt=1V VDD=15V Hitung (rancang) nilai resistansi yang diperlukan untuk ID=0,5mA Apayang terjadi bila Vt naik menjadi 1,5V? Gunakan thumb rule untuk menen- tukan tegangan drain-source Hitung resistor di source dan drain Hitung tegangan overdrive yang diperlukan 2 1 3 1 2 sedr42021_0431.jpg Figure 4.31 Circuit for Example 4.9. Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh 4. Hitung tegangan gate-source 5. Hitung tegangan gate 2 6 1 5 6. Hitung (pilih) resistor pembagi tegangan gate 5 4 3 1 6 2 sedr42021_0431.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

Contoh Tegangan threshold naik menjadi 1,5V Tegangan gate tetap Gunakan rangkaian di source untuk menentukan tegangan gate-source Gunakan persamaan arus-tegangan FET untuk menentukan arus drain 1 3 2 sedr42021_0431.jpg Perubahan arus drain atau Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0432.jpg Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0433a.jpg Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I using a current mirror. Microelectronic Circuits - Fifth Edition Sedra/Smith

saturasi Untuk atau Untuk sinyal kecil sehingga dapat ditulis dengan sedr42021_0434.jpg Untuk sinyal kecil sehingga dapat ditulis dengan atau Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0435.jpg Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier. Microelectronic Circuits - Fifth Edition Sedra/Smith

Untuk sinyal kecil Penguatan tegangan sedr42021_0436.jpg Figure 4.36 Total instantaneous voltages vGS and vD for the circuit in Fig. 4.34. Microelectronic Circuits - Fifth Edition Sedra/Smith

Penguatan tegangan Penguatan tegangan sedr42021_0437a.jpg Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in saturation (the channel-length modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID. Microelectronic Circuits - Fifth Edition Sedra/Smith

1 Menentukan titik kerja Kapasitor kopling untuk memisahkan tegangan DC kn’(W/L)=0,25mA/V2 Vt=1,5V VA=50V 1 Menentukan titik kerja arus drain untuk MOSFET saturasi tegangan drain hubungan tegangan drain dan gate sehingga dan dapat diperoleh Langkah analisis Tentukan titik kerja DC (quotient) Hitung parameter model ekivalen rangkaian sinyal kecil Susun rangkaian ekivalen sinyal kecil Lakukan analisis rangkaian sedr42021_0438a.jpg Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model. Microelectronic Circuits - Fifth Edition Sedra/Smith

2 Menghitung parameter model rangkaian ekivalen kn’(W/L)=0,25mA/V2 Vt=1,5V VA=50V 2 Menghitung parameter model rangkaian ekivalen Langkah analisis Tentukan titik kerja DC (quotient) Hitung parameter model ekivalen rangkaian sinyal kecil Susun rangkaian ekivalen sinyal kecil Lakukan analisis rangkaian sedr42021_0438a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

3 Menyusun rangkaian ekivalen sinyal kecil kn’(W/L)=0,25mA/V2 Vt=1,5V VA=50V 3 Menyusun rangkaian ekivalen sinyal kecil Sumber tegangan DC menjadi hubung singkat Kapasitor (tak hingga!) menjadi hubung singkat Langkah analisis Tentukan titik kerja DC (quotient) Hitung parameter model ekivalen rangkaian sinyal kecil Susun rangkaian ekivalen sinyal kecil Lakukan analisis rangkaian sedr42021_0438a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

4 Melakukan analisis rangkaian kn’(W/L)=0,25mA/V2 Vt=1,5V VA=50V 4 Melakukan analisis rangkaian tegangan output dengan pengaruh RG diabaikan penguatan tegangan sedr42021_0438a.jpg Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0439.jpg Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted but can be added between D and S in the T model of (d). Microelectronic Circuits - Fifth Edition Sedra/Smith

Model T MOSFET sedr42021_0440a.jpg Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0441a.jpg Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_tb0402a.jpg Table 4.2 Microelectronic Circuits - Fifth Edition Sedra/Smith

Rangkaian dasar (DC) penguat dengan MOSFET sedr42021_0442.jpg Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_e0430a.jpg Figure E4.30 Microelectronic Circuits - Fifth Edition Sedra/Smith

Definisi model “makro” penguat Penguatan tegangan beban terbuka Penguatan tegangan keseluruhan beban terbuka Penguatan tegangan Penguatan tegangan keseluruhan Penguatan arus beban hubung singkat sedr42021_tb0403a.jpg Penguatan arus Table 4.3 Microelectronic Circuits - Fifth Edition Sedra/Smith

Definisi model “makro” penguat Resistansi input tanpa beban Resistansi output “riil” Resistansi input Resistansi output sedr42021_tb0403a.jpg Transkonduktansi hubung singkat Table 4.3 Microelectronic Circuits - Fifth Edition Sedra/Smith

Definisi model “makro” penguat sedr42021_tb0403a.jpg Table 4.3 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0443a.jpg Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0444a.jpg Figure 4.44 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equivalent circuit with ro neglected. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0445a.jpg Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0446a.jpg Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. (c) Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_tb0404a.jpg Table 4.4 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_tb0404c.jpg Table 4.4 (Continued) Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0447a.jpg Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with Cdb neglected (to simplify analysis). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0448.jpg Figure 4.48 Determining the short-circuit current gain Io /Ii. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_tb0405.jpg Table 4.5 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0449a.jpg Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a) delineating the three frequency bands of interest. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0450a.jpg Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output; Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0450c.jpg Figure 4.50 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0451.jpg Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, ro is neglected. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0452.jpg Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are sufficiently separated for their effects to appear distinct. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0453.jpg Figure 4.53 The CMOS inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0454a.jpg Figure 4.54 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0455a.jpg Figure 4.55 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0456.jpg Figure 4.56 The voltage transfer characteristic of the CMOS inverter. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0457a.jpg Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through QN; (d) equivalent circuit during the capacitor discharge. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0458.jpg Figure 4.58 The current in the CMOS inverter versus the input voltage. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0459a.jpg Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0460a.jpg Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which Vt = –4 V and k¢n(W/L) = 2 mA/V2: (a) transistor with current and voltage polarities indicated; (b) the iD–vDS characteristics; (c) the iD–vGS characteristic in saturation. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0461.jpg Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the saturation regions. The case shown is for operation in the enhancement mode (vGS is positive). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0462.jpg Figure 4.62 Sketches of the iD–vGS characteristics for MOSFETs of enhancement and depletion types, of both polarities (operating in saturation). Note that the characteristic curves intersect the vGS axis at Vt. Also note that for generality somewhat different values of |Vt| are shown for n-channel and p-channel devices. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_e0451.jpg Figure E4.51 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_e0452.jpg Figure E4.52 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0463.jpg Figure 4.63 Capture schematic of the CS amplifier in Example 4.14. Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_0464.jpg Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with CS = 10 mF and CS = 0 (i.e., CS removed). Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04018a.jpg Figure P4.18 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04033a.jpg Figure P4.33 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04036.jpg Figure P4.36 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04037.jpg Figure P4.37 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04038.jpg Figure P4.38 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04041.jpg Figure P4.41 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04042a.jpg Figure P4.42 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04043a.jpg Figure P4.43 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04044a.jpg Figure P4.44 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04045.jpg Figure P4.45 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04046a.jpg Figure P4.46 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04047.jpg Figure P4.47 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04048.jpg Figure P4.48 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04054.jpg Figure P4.54 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04061.jpg Figure P4.61 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04066.jpg Figure P4.66 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04074.jpg Figure P4.74 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04075.jpg Figure P4.75 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04077.jpg Figure P4.77 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04086.jpg Figure P4.86 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04087.jpg Figure P4.87 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04088a.jpg Figure P4.88 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04097.jpg Figure P4.97 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04099.jpg Figure P4.99 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04101.jpg Figure P4.101 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04104.jpg Figure P4.104 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04117.jpg Figure P4.117 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04120.jpg Figure P4.120 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04121a.jpg Figure P4.121 Microelectronic Circuits - Fifth Edition Sedra/Smith

sedr42021_p04123.jpg Figure P4.123 Microelectronic Circuits - Fifth Edition Sedra/Smith