1 Pertemuan 21 Arithmetic: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan berbagai jenis operasi aritmatika didalam sistem komputer digital ( C4 ) ( No TIK : 10 )

3 Chapter 6. Arithmetic: I (OFC5)

4 s i = c i +1 = Figure 6.1. Logic specification for a stage of binary addition Y Example: 1 0 == Legend for stagei x i y i Carry-inc i Sums i Carry-outc i+1 X Z x i y i s i Carry-out c i+1 Carry-in c i x i y i c i x i y i c i x i y i c i x i y i c i x i y i c i  = +++ y i c i x i c i x i y i ++

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7 Figure 6.8. Sign extension of negative multiplicand  13-  143-  11+ () Sign extension is shown in blue

8 Figure 6.9. Normal and Booth multiplication schemes 's complement of the multiplicand

9 Figure Booth recoding of a multiplier

10 Figure Booth multiplication with a negative multiplier  13+()  78- 

11 Multiplier Biti i 1 - Version of multiplicand selected by biti M  1+M  1  M  0M  Figure Booth multiplier recoding table.

12 Figure Booth recoded multipliers Worst-case multiplier Ordinary multiplier Good multiplier

13 Pertemuan 22 Arithmetic: II Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

14 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Membandingkan berbagai jenis operasi aritmatika didalam sistem komputer digital ( C4 ) ( No TIK : 10 )

15 Chapter 6. Arithmetic: II (OFC6)

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17 Figure Ripple-carry and carry-save arrays for the multiplication operation M  Q = P for 4-bit operands.

18 Figure A multiplication example used to illustrate carry-save addition as shown in Figure M Q A B C D E F (2,835) X (45) (63) Product

19 Figure Schematic representation of the carry-save addition operations in Figure 6.18.

20 Figure Longhand division examples

21 q n1- m n1- -bit Divisor M Control sequencer Dividend Q Shift left adder a n1- a 0 q 0 m 0 a n 0 Add/Subtract Quotient setting n1+ Figure Circuit arrangement for binary division. A

(a) Unnormalized value (b) Normalized version (There is no implicit 1 to the left of the binary point.) Value represented  2 9  +=... Value represented  2 6  += Figure Floating-point normalization in IEEE single-precision format. excess-127 exponent

23 RepresentationExamples Sign and magnitude 9's complement 10's complement Figure P6.1. Signed numbers in base 10 used in Problem   70

24 12 bits 5 bits excess-15 exponent 6 bits fractional mantissa 1 bit for sign of number Figure P6.2. Floating-point format used in Problem signifies -1 signifies

25 Figure P6.3. 1's-complement addition used in Problem (3) ( (6) ( ) 2- 3-)