Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI

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1 Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI
Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01 Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI

2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan struktur logik gerbang CMOS-VLSI.

3 Mirror circuits are based on series-parallel
logic gates, but usually faster and have a more uniform layout A B F A B F F = A  B On device nFET pFET

4 Mirror Circuits Gnd a b VDD Layout VDD a b a  b Rangkaian

5 Mirror Circuits Rp Cp Cout Rn Cn  : time constant r : rise time
f : fall time

6 Struktur umum pseudo nMOS
VDD Pull-up Load nFET Logic Array Pull-down + - VSGp f Struktur umum pseudo nMOS p n VOL Pseudo nMOS inverter

7 Rangkaian CMOS Tri-state
Rangkaian Tri-state Data En f En f Z Data Gnd Layout En VDD f Data VDD Data En f Rangkaian CMOS Tri-state Mp Mn M1 M2

8 Struktur clock gerbang CMOS
Clocked CMOS 1 T 2T  time Struktur clock gerbang CMOS a f(a, b, c) M1 M2 nFET pFET b c Vout + - Cout VDD Input valid Hi-Z

9 Clocked CMOS Rangkaian NAND2 Layout VDD Mp  M1 a . b Cout M2 a Mn b
Gnd Layout Out

10 Dynamic CMOS LOGIC A dynamic logic gate uses clocking and charge
storage properties of MOSFETs to implement logic operations Basic dynamic gate logic VDD Mp a Mn  nFET b c d Cout Vout f Precharge Mp ON Mn OFF Evaluate Mp OFF Mn ON T

11 Contoh rangkaian dynamic logik
Dynamic CMOS LOGIC Contoh rangkaian dynamic logik VDD b  a Mp c Cout f Mn Vout Layout Gnd

12 Dual Rail Logic We have been concentrating on single-rail logic Circuits where the value of a variables is eiher a 0 or 1 only. In dual-rail networks, both the variable x and its complement x are used to form the difference fx = (x – x )

13 Structure of a CVSL logic gate
Dual Rail Logic Vr VDD Vl a MP2 MP1 b c Sw1 Sw2 Logic tree f Latch Vr VDD Vl a . b a b AND / NAND Structure of a CVSL logic gate

14 RESUME Mirror Circuiuts. Pseudo nMOS. Tri-state. Clocked CMOS. Dynamic CMOS Logic. Dual Rail Logic.