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1 Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01.

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Presentasi berjudul: "1 Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01."— Transcript presentasi:

1 1 Pertemuan 8 Struktur Logik Gerbang CMOS-VLSI Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01

2 2 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan struktur logik gerbang CMOS-VLSI.

3 3 Mirror Circuits Mirror circuits are based on series-parallel logic gates, but usually faster and have a more uniform layout A B F A B F F = A  B On device nFET pFET nFET

4 4 Mirror Circuits V DD a b a b a b a b a  b Rangkaian Gnd ab ab VDD Layout

5 5 Mirror Circuits RpRp RpRp RnRn RnRn CnCn CpCp RpRp RpRp RnRn RnRn CnCn CpCp C out  : time constant r : rise time f : fall time

6 6 Pseudo nMOS V DD Pull-up Load nFET Logic Array Pull-down + - V SGp f Struktur umum pseudo nMOS V DD pp nn V OL V DD Pseudo nMOS inverter

7 7 Rangkaian Tri-state Data En f En f 0 Z 1 Data V DD Data En f Rangkaian CMOS Tri-state MpMp MnMn M1M1 M2M2 Gnd Layout En VDD f Data

8 8 Clocked CMOS 1 1 0T 2T   time Struktur clock gerbang CMOS a   f(a, b, c) M1M1 M2M2 nFET pFET b c a b c V out + - C out V DD Input valid Hi-Z 

9 9 Clocked CMOS Rangkaian NAND2 V DD a   MpMp MnMn M1M1 M2M2 b a b C out a. b Gnd Layout b VDD  Out a 

10 10 Dynamic CMOS LOGIC Basic dynamic gate logic V DD Mp a Mn  nFET b c d C out V out f  Precharge Mp ON Mn OFF Precharge Mp ON Mn OFF Evaluate Mp OFF Mn ON T A dynamic logic gate uses clocking and charge storage properties of MOSFETs to implement logic operations

11 11 Dynamic CMOS LOGIC Contoh rangkaian dynamic logik V DD b  a MpMp c C out f MnMn V out Layout Gnd VDD f b c a 

12 12 Dual Rail Logic We have been concentrating on single-rail logic Circuits where the value of a variables is eiher a 0 or 1 only. In dual-rail networks, both the variable x and its complement x are used to form the difference fx = (x – x )

13 13 Dual Rail Logic VrVr V DD VlVl a MP2 MP1 b c a b c Sw1 Sw2 Logic tree f f Latch Structure of a CVSL logic gate VrVr V DD VlVl a. b a b AND / NAND a b

14 14 RESUME Mirror Circuiuts. Pseudo nMOS. Tri-state. Clocked CMOS. Dynamic CMOS Logic. Dual Rail Logic.


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